cva6 学习笔记0

更新中,有问题,完成更新后删除。

按照原文章中的描述,cva6是一个6级流水线、顺序、单发射、64bit处理器,它完整的实现了非特权手册中的I64MAFDC指令集,以及特权手册中的MSU特权等级,以支持类Unix操作系统。

但在理解代码时,遇到了很多问题,在这里把问题记录一下,欢迎大家一起讨论。

一、Frontend

这里按框图来看是分成了两级流水。但我理解是四级流水,分别是pc_gen,读指,预测,指令缓存。

1.1pc_gen

分为两部分描述:

取指

pc-select 有7种情况,详情翻阅其他相关帖子介绍。

取指地址32bit对齐,忽略低2位(取指位宽可选的,这里按32bit取指位宽分析)。

当不发生跳转时,指令地址是非32bit对齐时(只会发生在地址跳转后的第一笔),next_pc=pc+2,注意由于取指地址32bit对齐,且存在压缩指令的情况,在预测逻辑中有一个re-align的模块,用来解决这些问题。详细见re-align模块。

预测逻辑的输入来读指流水的输出,但取指不会因为预测而阻塞,可以看做是在取指阶段先静态预测为所有指令都不发生跳转,等到预测流水阶段要token时,再flush掉前面两级流水。

1.2读指

与cache的接口是双通道的所以支持将取指阶段流水起来。

命中时在下一个cycle后返回数据

1.3预测

逻辑顺序为:re-align -> scan -> 预测

1.3.1 re-align

地址32对齐有无缓存指令[1:0]指令[17:16]输出指令valid缓存部分指令在re-align模块,用于与下一笔的拼接
10非压缩-2'b01-
10压缩非压缩2‘b01[31:16]
10压缩压缩2‘b11-
11-非压缩2‘b01[31:16] 
11-压缩2‘b11’-
0-非压缩-2'b00[15:0] (模块外已经从高位右移到低位)
0-压缩-2'b01-

1.3.2 scan

微解码模块。

对两条指令并行微解码。

1.3.3 预测

预测方向BHT

预测地址 RAS/BTB

指令有两种情况:2'b01,2'b11。当2'b11时,低指令有更高优先级。

1.4 缓存

当发生预测时, 预测指令后的指令失效,比如 输入指令是2‘b11 ,高指令是预测有效指令,则两条指令仍然都有效,输入指令是2‘b11 ,低指令是预测有效指令,则只有低指令有效(代码中的lzc...branch_mask做了这段逻辑)。

写时,通过idx_is_q的这段逻辑 保证写入两个fifo的顺序正确。

读时,两个fifo乒乓读取。

预测地址、读指令异常等会随预测指令一起流到后续流水中。

The RISC-V CVA6 core is a compact, low-power processor core that is designed to be used in microcontrollers and other embedded systems. It is based on the RISC-V ISA (Instruction Set Architecture), which is an open, royalty-free standard that allows anyone to design and implement their own processor cores. The CVA6 core is designed to be highly configurable, allowing users to customize it to meet their specific needs. It supports the RV32I base instruction set, as well as a number of optional extensions, including the M (integer multiplication and division) extension, the F (single-precision floating-point) extension, and the D (double-precision floating-point) extension. One of the key features of the CVA6 core is its low power consumption. It is designed to be used in battery-powered devices and other low-power applications, and it includes a number of power-saving features, such as dynamic voltage and frequency scaling, that help to reduce power consumption even further. The CVA6 core is also highly scalable, making it suitable for use in a wide range of applications. It can be used as a standalone processor in a microcontroller or embedded system, or it can be integrated into a larger system-on-chip (SoC) design. Overall, the RISC-V CVA6 core is an excellent choice for anyone looking for a low-power, highly configurable processor core for use in microcontrollers and other embedded systems. Its open, royalty-free design makes it an attractive alternative to proprietary processor architectures, and its high level of configurability makes it easy to customize to meet specific application requirements.
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