整理MTK dsi.PLL_CLOCK配置

本文详细介绍了DSI(Display Serial Interface)在不同模式下数据速率的计算方法,并提供了具体的计算实例。同时,文中还解释了如何根据计算出的数据速率来设置Clock频率。

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DSI采用的是双边采样,则clk等于数据速率的一半,也就是说一个clk周期内传送2位,所以你计算出来的值还要除以2
根据mtk faq的计算公式,是这样的:

1、DSI vdo mode下的数据速率data_rate的大致计算公式为:
Data rate= (Height+VSA+VBP+VFP)*(Width+HSA+HBP+HFP)* total_bit_per_pixel*frame_per_second/total_lane_num

2、DSI cmd mode下的数据速率data_rate的大致计算公式为:
Data rate= width*height*1.2* total_bit_per_pixel*frame_per_second/total_lane_num

每线 clk =  Data rate/2;

Data Rate,即Data Lane上数据传输速率,在VDO MODE中计算公式如下:

Data Rate = ((height + vsa + vbp + vfp) * (width + hsa + hbp + hfp) *
	bits_per_pixel * frames_per_second) / data_lanes

例如:
Data Rate = ((960 + 4 + 16 + 16) * (540 + 4 + 40 + 40) * 24 * 60) / 2 = 418798080
即Data Rate约为420MHz

而dsi在clock的上升沿和下降沿都会采集数据,所以在计算clock时应为Data Rate的一半,对应前面的420MHz,那么clock应设置为210MHz(注意在计算clock时,clock * 2应比Data Rate稍大)。

那么在mtk平台上应该如何设置clock的频率呢?有两种方式,一是通过配置3个参数得到(6582 kk平台),二是直接设置clock频率(推荐第二种)。
第一种方式,通过分频倍频计算:
params->dsi.pll_div1 = 1;	/* 配置0,1,2,3时对应的div1_real为1,2,4,4 */
params->dsi.pll_div2 = 1;	/* 配置0,1,2,3时对应的div2_real为1,2,4,4 */
params->dsi.fbk_div = 30;	/* 范围是0~63 */
那么输出频率计算公式如下:
(26MHz * (fbk_div + 1) * 2) / (div1_real * div2_real) = (26 * 31 * 2) / (2 * 2) = 403。
那么这种方式实际上计算出来是的Data Rate,即mtk手册上所说的BRPL(Bits Rate Per Lane)。

第二种方式:
params->dsi.PLL_CLOCK = 210MHz;

从代码看来,实际上他们最后都是通过设置DSI_PLL_CON0和DSI_PLL_CON2寄存器来实现的。

参考文档:MT6582_LCM_Porting_Guide_DSI_V1.0.pptx.pdf
	MTK_on_line_FAQ_SW_ALPS_20141031.pdf
### PLL Clock in Digital Electronics and FPGA Design In digital electronics and Field Programmable Gate Array (FPGA) design, Phase-Locked Loops (PLLs) play a crucial role in generating stable clock signals with precise frequency control. A PLL is an electronic circuit that generates an output signal whose phase is related to the phase of an input reference signal. #### Functionality of PLLs A typical PLL consists of three main components: a phase detector, a low-pass filter, and a voltage-controlled oscillator (VCO). The function of these components can be summarized as follows: - **Phase Detector**: Compares the phases of the input reference signal and feedback signal. - **Low-Pass Filter**: Smoothens out rapid changes from the phase detector's output. - **Voltage-Controlled Oscillator (VCO)**: Generates an oscillating output based on the filtered error signal provided by the low-pass filter[^1]. When used within FPGAs, PLLs provide several advantages including jitter reduction, frequency synthesis capabilities, and improved timing margins which enhance overall system reliability and performance. #### Source Latency Considerations Source latency refers specifically to the propagation delay encountered when transmitting a clock signal from its origin point such as a PLL or crystal oscillator until reaching designated points where clocks are utilized inside circuits or systems[^2]. This parameter becomes particularly important during high-speed designs because any discrepancy between actual arrival times at different locations could lead to potential setup/hold violations impacting functionality negatively. To mitigate issues arising due to source latencies especially concerning off-chip elements like external crystals connected via PCB traces; careful planning around trace lengths alongside employing techniques aimed at minimizing variations across multiple paths should be considered essential practices. #### Types of Clock Skew Impacting System Performance Clock skews refer broadly speaking about inconsistencies present amongst various parts receiving supposedly synchronized pulses emanated originally through one common master clock generator but experiencing differing delays along their respective routes leading up till destination registers/logic blocks etc., thereby causing misalignment problems among operations supposed otherwise occur concurrently under ideal conditions without discrepancies whatsoever existing beforehand regarding relative timings involved hereof[^3]. Two primary categories exist herein namely intrinsic & extrinsic ones – while former pertains directly towards inherent characteristics associated inherently within individual devices themselves constituting part thereof i.e., internal structure/configuration aspects affecting distribution internally only thus far beyond user intervention scope practically speaking most often than not unless specific measures taken explicitly targeting mitigation efforts against same effect post-fabrication stage perhaps using calibration routines built-in possibly available sometimes depending upon make/model specifics chosen initially before deployment even starts really getting underway properly yet still limited extent generally applicable nonetheless compared wherewith latter category meanwhile encompasses everything outside aforementioned boundaries therefore covering all other possible sources contributing factor(s), mainly focusing primarily over physical layout arrangements made externally surrounding interconnections established therebetween diverse constituents forming complete assembly altogether instead now falling squarely into domain area controllable more readily enough usually once proper attention paid accordingly throughout entire process lifecycle stages starting right away early conceptualization/planning phases moving forward progressively stepwise manner eventually culminating final implementation realization ultimately achieved successfully hopefully after thorough testing/validation cycles completed satisfactorily indeed confirming expected behavior observed consistently every single instance tried repeatedly under varying operational scenarios tested exhaustively ensuring robustness maintained reliably regardless environmental factors potentially influencing outcomes adversely somehow somewhere somehow sometime someday someway somewhat... ```python # Example Python code demonstrating basic usage of PLL configuration in Xilinx Vivado HLS environment def configure_pll(input_frequency_mhz, desired_output_frequencies): """ Configures a PLL to generate specified frequencies Args: input_frequency_mhz (float): Input frequency in MHz desired_output_frequencies (list[float]): List of target output frequencies Returns: dict: Configuration parameters for each output channel """ config = {} vco_freq = max(desired_output_frequencies) * 2 # Ensure VCO freq higher than highest required output for idx, f_out in enumerate(desired_output_frequencies): div_ratio = int(vco_freq / f_out) config[f'output_{idx}'] = { 'vco_multiplier': round(vco_freq / input_frequency_mhz), 'divider': div_ratio, 'actual_output_freq': vco_freq / div_ratio } return config ```
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