verilog ——Module fadd

描述：

In this exercise, you will create a circuit with two levels of hierarchy. Your top_module will instantiate two copies of add16 (provided), each of which will instantiate 16 copies of add1 (which you must write). Thus, you must write two modules: top_module and add1.

Like module_add, you are given a module add16 that performs a 16-bit addition. You must instantiate two of them to create a 32-bit adder. One add16 module computes the lower 16 bits of the addition result, while the second add16 module computes the upper 16 bits of the result. Your 32-bit adder does not need to handle carry-in (assume 0) or carry-out (ignored).

Connect the add16 modules together as shown in the diagram below. The provided module add16 has the following declaration:

module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );

Within each add16, 16 full adders (module add1, not provided) are instantiated to actually perform the addition. You must write the full adder module that has the following declaration:

module add1 ( input a, input b, input cin, output sum, output cout );

Recall that a full adder computes the sum and carry-out of a+b+cin.

In summary, there are three modules in this design:

• top_module — Your top-level module that contains two of...
• add16, provided — A 16-bit adder module that is composed of 16 of...
• add1 — A 1-bit full adder module.

If your submission is missing a module add1, you will get an error message that says Error (12006): Node instance "user_fadd[0].a1" instantiates undefined entity "add1".

 

 

 代码如下：

module top_module (
    input wire [31:0] a,
    input wire [31:0] b,
    output reg [31:0] sum
);//
    wire [15:0] a1,b1,a2,b2;
    wire [15:0] add1,add2;
    wire c161;
    add16 inst161(.a(a1),.b(b1),.cin(0),.sum(add1),.cout(c161));
    add16 inst162(.a(a2),.b(b2),.cin(c161),.sum(add2));
    assign a1=a[15:0];
    assign a2=a[31:16];
    assign b1=b[15:0];
    assign b2=b[31:16];    
    assign sum={add2,add1};
endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );
// Full adder module here
    reg [1:0] sumaa; 
     
    always @(*)
	begin 
        sumaa = cin+a+b;
    end
    assign cout=sumaa[1];
    assign sum =sumaa[0];
endmodule

/*module add16 ( input[15:0] a, input[15:0] b, input cin, output[15:0] sum, output cout );
// Full adder module here
    wire sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8,sum9,sum10,sum11,sum12,sum13,sum14,sum15,sum16;
    wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15,c16;
    //wire [15:0] sum16_1,sum16_2;
    wire [15:0] a1,b1;
    add1 inst1(.a(a1[0]),.b(b1[0]),.cin(0),.sum(sum1),.cout(c1));
    add1 inst2(.a(a1[1]),.b(b1[1]),.cin(c1),.sum(sum2),.cout(c2));
    add1 inst3(.a(a1[2]),.b(b1[2]),.cin(c2),.sum(sum3),.cout(c3));
    add1 inst4(.a(a1[3]),.b(b1[3]),.cin(c3),.sum(sum4),.cout(c4));
    add1 inst5(.a(a1[4]),.b(b1[4]),.cin(c4),.sum(sum5),.cout(c5));
    add1 inst6(.a(a1[5]),.b(b1[5]),.cin(c5),.sum(sum6),.cout(c6));
    add1 inst7(.a(a1[6]),.b(b1[6]),.cin(c6),.sum(sum7),.cout(c7));
    add1 inst8(.a(a1[7]),.b(b1[7]),.cin(c7),.sum(sum8),.cout(c8));
    add1 inst9(.a(a1[8]),.b(b1[8]),.cin(c8),.sum(sum9),.cout(c9));
    add1 inst10(.a(a1[9]),.b(b1[9]),.cin(c9),.sum(sum10),.cout(c10));
    add1 inst11(.a(a1[10]),.b(b1[10]),.cin(c10),.sum(sum11),.cout(c11));
    add1 inst12(.a(a1[11]),.b(b1[11]),.cin(c11),.sum(sum12),.cout(c12));
    add1 inst13(.a(a1[12]),.b(b1[12]),.cin(c12),.sum(sum13),.cout(c13));
    add1 inst14(.a(a1[13]),.b(b1[13]),.cin(c13),.sum(sum14),.cout(c14));
    add1 inst15(.a(a1[14]),.b(b1[14]),.cin(c14),.sum(sum15),.cout(c15));
    add1 inst16(.a(a1[15]),.b(b1[15]),.cin(c15),.sum(sum16),.cout(c16));
   
    assign sum={sum16,sum15,sum14,sum13,sum12,sum11,sum10,sum9,sum8,sum7,sum6,sum5,sum4,sum3,sum2,sum1};
endmodule
*/