linux qcom LCD framwork --- Good

本文详细介绍了MDSS(多媒体显示子系统)和DSI(显示串行接口)的工作原理,涵盖了核心层、MDSS核心层、MDP、DSI、LCD驱动等关键组件的文件及函数,解析了时序图、重要结构赋值过程,以及LCD配置的传递方式。同时,文章探讨了fb旋转参数配置、展频、GPIO控制、ESD功能等内容。
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come from : https://blog.youkuaiyun.com/u012719256/article/details/52096727

0.关键字
MDSS : Multimedia Display sub system 
DSI: Display Serial Interface

qcom,mdss-dsi-force-clock-lane-hs;          // faulse :clock每帧回lp11   ture: clock不回
qcom,mdss-dsi-hfp-power-mode;               // data 每行回lp11,对应的hfp要修改成300以上
 
1.涉及文件
(1) drivers\video\fbmem.c (核心层)

  register_framebuffer(struct fb_info *fb_info)   //对外暴露核心函数
 
(2)drivers\video\msm\mdss\mdss_fb.c (mdss 核心层 fbx平台设备驱动)

// 调用 fbmem.c的 register_framebuffer注册 fbx
 
(4)msm8610-mdss.dtsi (文件名通常为 msmxxx-mdss.dtsi 指定了mdss 的 mdp 和 dsi)

  mdss_mdp: qcom,mdss_mdp@fd900000 {
            compatible = "qcom,mdss_mdp3";  // 对应mdss驱动 mdss_mdp.c


----------


  mdss_dsi0: qcom,mdss_dsi@fdd00000 {
        compatible = "qcom,msm-dsi-v2";      // 对应dsi解析驱动 dsi_host_v2.c

或者

  mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 {
        compatible = "qcom,mdss-dsi-ctrl";  // 对应dsi解析驱动 mdss_dsi.c
 
(3)drivers\video\msm\mdss\dsi_host_v2.c (lcd驱动 dsi)

// 通过下面函数向 mdss_fb.c 注册了fb_info结构  (包含在mdss_dsi_ctrl_pdata结构中)
dsi_panel_device_register_v2(struct platform_device *dev,struct mdss_dsi_ctrl_pdata *ctrl_pdata)


static const struct of_device_id msm_dsi_v2_dt_match[] = {
    {.compatible = "qcom,msm-dsi-v2"},
    {}
};
 
或者 
drivers\video\msm\mdss\mdss_dsi.c

(5)drivers\video\msm\mdss\mdp3.c (mdp)

   .compatible = "qcom,mdss_mdp3",

 
(6)msm8610-asus.dts (指定mdp中的哪一个配置) 
通常在dts文件的 mdss_dsi0 lab里面通过 qcom,dsi-pref-prim-pan 属性 指定使用哪一个lcd配置

&mdss_dsi0 {
        qcom,dsi-pref-prim-pan = <&dsi_fl10802_fwvga_vid>;
};
 
(7)dsi-panel-fl10802-fwvga-video.dtsi

&mdss_mdp {
    dsi_fl10802_fwvga_vid: qcom,mdss_dsi_fl10802_fwvga_video {
        qcom,mdss-dsi-panel-name = "fl10802 fwvga video mode dsi panel";
        qcom,mdss-dsi-drive-ic = "fl10802";
        qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
        qcom,mdss-dsi-panel-type = "dsi_video_mode";
        qcom,mdss-dsi-panel-destination = "display_1";
        ...
        }
 
2. mdss_mdp 和 mdss_dsi0 的关系
mdss_mdp 相当于一个数组,里面定义了很多不同lcd显示屏的配置项包括分辨率等等

mdss_dsi0 的 “qcom,dsi-pref-prim-pan ” 属性指定了使用mdss_mdp中哪一个lcd配置选项 


3.时序图
http://download.youkuaiyun.com/detail/u012719256/9603691 
画的有点渣,凑活看吧,不要在意细节   


4. 重要结构
结构关系

backLight
关键字:qcom,mdss-dsi-bl-pmic-control-type
 

struct mdss_dsi_ctrl_pdata {
    int ndx;    /* panel_num */
    int (*on) (struct mdss_panel_data *pdata);                              // ★ on
    int (*off) (struct mdss_panel_data *pdata);                             // ★ off
    int (*partial_update_fnc) (struct mdss_panel_data *pdata);
    int (*check_status) (struct mdss_dsi_ctrl_pdata *pdata);
    int (*cmdlist_commit)(struct mdss_dsi_ctrl_pdata *ctrl, int from_mdp);
    void (*switch_mode) (struct mdss_panel_data *pdata, int mode);
    struct mdss_panel_data panel_data;                          //★  panel_data.set_backlight   设置背光亮度函数
                                                                //★  panel_data.panel_info    = struct mdss_panel_info ①
    unsigned char *ctrl_base;
    struct dss_io_data ctrl_io;
    struct dss_io_data mmss_misc_io;
    struct dss_io_data phy_io;
    int reg_size;
    u32 bus_clk_cnt;
    u32 link_clk_cnt;
    u32 flags;
    struct clk *mdp_core_clk;
    struct clk *ahb_clk;
    struct clk *axi_clk;
    struct clk *mmss_misc_ahb_clk;
    struct clk *byte_clk;
    struct clk *esc_clk;
    struct clk *pixel_clk;
    u8 ctrl_state;
    int panel_mode; 
    int irq_cnt;
    int rst_gpio;                   // ★ gpio  qcom,platform-reset-gpio:        Specifies the panel reset gpio.
    int disp_en_gpio;               // qcom,platform-enable-gpio:               Specifies the panel lcd/display enable gpio.
    int disp_te_gpio;               // qcom,platform-te-gpio:                   Specifies the gpio used for TE.
    int mode_gpio;                  // qcom,platform-mode-gpio:             Select video/command mode of panel through gpio when it supports both modes.
    int disp_te_gpio_requested;
    int bklt_ctrl;                  /* backlight ctrl 背光类型*/   
    int pwm_period;
    int pwm_pmic_gpio;
    int pwm_lpg_chan;
    int bklt_max;
    int new_fps;
    int pwm_enabled;
    bool dmap_iommu_map;
    struct pwm_device *pwm_bl;
    struct dsi_drv_cm_data shared_pdata;
    u32 pclk_rate;
    u32 byte_clk_rate;
    struct dss_module_power power_data;     // ★ clock & regulator
    u32 dsi_irq_mask;
    struct mdss_hw *dsi_hw;
    struct mdss_panel_recovery *recovery;

    struct dsi_panel_cmds on_cmds;          // light on cmd  ★    qcom,mdss-dsi-on-command

    struct dsi_panel_cmds off_cmds;         // off cmd      ★    qcom,mdss-dsi-off-command
    struct dsi_panel_cmds status_cmds;
    u32 status_value;

    struct dsi_panel_cmds video2cmd;
    struct dsi_panel_cmds cmd2video;

    struct dcs_cmd_list cmdlist;
    struct completion dma_comp;
    struct completion mdp_comp;
    struct completion video_comp;
    struct completion bta_comp;
    spinlock_t irq_lock;
    spinlock_t mdp_lock;
    int mdp_busy;
    struct mutex mutex;
    struct mutex cmd_mutex;

    bool ulps;

    struct dsi_buf tx_buf;
    struct dsi_buf rx_buf;
    struct dsi_buf status_buf;
    int status_mode;
};
 
① struct mdss_panel_info


struct mdss_panel_info {
    u32 xres;                   // x 分辨率     qcom,mdss-dsi-panel-width
    u32 yres;                   // y 分辨率        qcom,mdss-dsi-panel-height
    u32 physical_width;         // x 物理大小   qcom,mdss-pan-physical-width-dimension
    u32 physical_height;        // y 物理大小   qcom,mdss-pan-physical-height-dimension
    struct lcd_panel_info lcdc; // 边界       (1.1)边界
    u32 bpp;                    // bpp          qcom,mdss-dsi-bpp
    struct mipi_panel_info mipi; // mipi显示模式 video or cmd  (1.2)mipi

    u32 type;
    u32 wait_cycle;
    u32 pdest;                 // 第几个fb设备  qcom,mdss-dsi-panel-destination = "display_1";
    u32 brightness_max;
    u32 bl_max;
    u32 bl_min;
    u32 fb_num;
    u32 clk_rate;
    u32 clk_min;
    u32 clk_max;
    u32 frame_count;
    u32 is_3d_panel;
    u32 out_format;
    u32 rst_seq[MDSS_DSI_RST_SEQ_LEN];
    ...
    }
 
(1.1)边界


struct lcd_panel_info {
    u32 h_back_porch;
    u32 h_front_porch;
    u32 h_pulse_width;
    u32 v_back_porch;
    u32 v_front_porch;
    u32 v_pulse_width;
    u32 border_clr;
    u32 underflow_clr;
    u32 hsync_skew;
    /* Pad width */
    u32 xres_pad;       // qcom,mdss-dsi-h-left-border
    /* Pad height */
    u32 yres_pad;       // qcom,mdss-dsi-h-right-border
};

 
(1.2)mipi

struct mipi_panel_info {
    char mode;      /* video/cmd */   // 显示模式   qcom,mdss-dsi-panel-type = "dsi_video_mode";
    char interleave_mode;
    char crc_check;
    char ecc_check;
    char dst_format;    /* shared by video and command */
    char data_lane0;
    char data_lane1;
    char data_lane2;
    char data_lane3;
    char dlane_swap;    /* data lane swap */
    char rgb_swap;
    char b_sel;
    char g_sel;
    char r_sel;
    char rx_eot_ignore;
    char tx_eot_append;
    char t_clk_post; /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
    char t_clk_pre;  /* 0xc0, DSI_CLKOUT_TIMING_CTRL */
    char vc;    /* virtual channel */
    struct mdss_dsi_phy_ctrl dsi_phy_db;
    /* video mode */
    char pulse_mode_hsa_he;
    char hfp_power_stop;
    char hbp_power_stop;
    char hsa_power_stop;
    char eof_bllp_power_stop;
    char last_line_interleave_en;
    char bllp_power_stop;
    char traffic_mode;
    char frame_rate;
    /* command mode */
    char interleave_max;
    char insert_dcs_cmd;
    char wr_mem_continue;
    char wr_mem_start;
    char te_sel;
    char stream;    /* 0 or 1 */
    char mdp_trigger;
    char dma_trigger;
    /*Dynamic Switch Support*/
    bool dynamic_switch_enabled;
    u32 pixel_packing;
    u32 dsi_pclk_rate;
    /* The packet-size should not bet changed */
    char no_max_pkt_size;
    /* Clock required during LP commands */
    char force_clk_lane_hs;   //强制DSI_CLK始终处于HS,因我们用DSI CLK as 参考时钟

    char vsync_enable;
    char hw_vsync_mode;

    char lp11_init;
    u32  init_delay;
};
 
5.结构赋值
//结构从设备数中获取数据赋值     mdss_dsi_panel.c

int mdss_dsi_panel_init(struct device_node *node,struct mdss_dsi_ctrl_pdata *ctrl_pdata,    int ndx)

// use
Dsi_host_v2.c (drivers\video\msm\mdss): rc = mdss_dsi_panel_init(dsi_pan_node, ctrl_pdata, cmd_cfg_cont_splash);
Mdss_dsi.c (drivers\video\msm\mdss):            rc = mdss_dsi_panel_init(dsi_pan_node, ctrl_pdata, ndx);


 
6.lk中传递lcm使用的dsi配置名字给kernel

aboot_init                           // lk\app\aboot\aboot.c
    target_display_init         // lk\target\msm8953\target_display.c
        gcdb_display_init        // lk\dev\gcdb\display\gcdb_display.c
            msm_display_init  // display.c
                display_image_on_screen   //


aboot_init                           // lk\app\aboot\aboot.c
    target_display_init         // lk\target\msm8953\target_display.c
        gcdb_display_init        // lk\dev\gcdb\display\gcdb_display.c
            oem_panel_select   // lk\target\msm8953\oem_panel.c

            panel_id = NT51021B_INX_WUXGA_VIDEO_PANEL;    // ☆ panel_id 赋值,使用哪个lcd配置

                init_panel_data     

                    switch (panel_id) {
                            case NT51021B_INX_WUXGA_VIDEO_PANEL:
                                panelstruct->paneldata    = &nt51021b_inx_wuxga_video_panel_data;   // 根据 panel_id 指定传给kernel使用的lcm配置


----------

// lk\dev\gcdb\display\include\panel_nt51021b_inx_wuxga_video.h  (lcm配置文件)

static struct panel_config nt51021b_inx_wuxga_video_panel_data = {
  "qcom,mdss_dsi_nt51021b_inx_wuxga_video",    // ☆ panel_node_id 对应dtsi中 panel使用的名字 
  "dsi:0:", "qcom,mdss-dsi-panel",
  10, 0, "DISPLAY_1", 0, 0, 60, 0, 0, 0, 1, 10000, 0, 0, 0, 0, 0, 0, NULL
};                                


----------


// arch\arm64\boot\dts\qcom\dsi-panel-nt51021b-inx-wuxga-video.dtsi
&mdss_mdp {
    dsi_nt51021b_inx_wuxga_vid: qcom,mdss_dsi_nt51021b_inx_wuxga_video {//dts中的 panel名字
        qcom,mdss-dsi-panel-name = "nt51021b inx wuxga video mode dsi panel";  // 对应 sys/class/graphic/fb0/panl_info 中的信息
 
6.dts中command格式解析

qcom,mdss-dsi-on-command = [
         //            延时      reg data              
            29 01 00 00 01 00 02 8F A5
            29 01 00 00 14 00 02 01 00
            29 01 00 00 01 00 02 8F A5
            29 01 00 00 00 00 02 8C 80
            29 01 00 00 00 00 02 C7 50
            29 01 00 00 00 00 02 C5 50
            29 01 00 00 00 00 02 85 04
            29 01 00 00 00 00 02 86 08
            29 01 00 00 00 00 02 83 AA
            29 01 00 00 00 00 02 84 11
            29 01 00 00 00 00 02 A0 36
            29 01 00 00 00 00 02 A1 36
            29 01 00 00 00 00 02 9C 10
            29 01 00 00 00 00 02 A9 4B
            29 01 00 00 00 00 02 8F 00];
 
7.fb旋转参数配置
(1) 方法1

fb_info->var->rotate                             // 是否旋转
1
(2) 方法2


msm_fb_data_type->panel_orientation                  //是否旋转fb   (mdss_fb.h)

// 通过dsi中的 qcom,mdss-dsi-panel-orientation 关键字控制  (mdss_dsi_panel.c)
data = of_get_property(np, "qcom,mdss-dsi-panel-orientation", NULL);
    if (data) {
        pr_debug("panel orientation is %s\n", data);
        if (!strcmp(data, "180"))
            pinfo->panel_orientation = MDP_ROT_180;
        else if (!strcmp(data, "hflip"))
            pinfo->panel_orientation = MDP_FLIP_LR;
        else if (!strcmp(data, "vflip"))
            pinfo->panel_orientation = MDP_FLIP_UD;
    }

 
(3)方法三 
system/build.prop 
+ ro.panel.mountflip=3

frameworks/native/services/surfaceflinger/DisplayDevice.cpp
DisplayDevice::DisplayDevice

  // 1: H-Flip, 2: V-Flip, 3: 180 (HV Flip)
      property_get("ro.panel.mountflip", property, "0");
      mPanelMountFlip = atoi(property);
 
8.展频

    mdss-pll.c

    展频开关:

    arch/arm/boot/dts/qcom/msm8953-mdss-pll.dtsi   qcom,dsi-pll-ssc-en;

    mode:

    qcom,dsi-pll-ssc-mode = "down-spread";

    two parameters to program SSC :

    clk/msm/mdss/mdss-dsi-pll-8996.c:ssc_ppm_default & ssc_freq_default

    展频范围:

    down mode : freq - freq * (ssc_ppm/1000,000)

    center mode : freq ± freq * (ssc_ppm/1000,000) / 2

    up mode : freq + freq * (ssc_ppm/1000,000)
 
9.bklt_en_gpio、 disp_en_gpio、 rst_gpio相关gpio口

// (msm8917-pmi8937-qrd-sku5.dtsi  board.dtsi )   mdss_dsi_active   mdss_dsi_suspend  qcom,platform-reset-gpio  qcom,platform-enable-gpio
&mdss_dsi0 {  
    qcom,dsi-pref-prim-pan = <&dsi_hx8394f_720p_video>;
    pinctrl-names = "mdss_default", "mdss_sleep";
    pinctrl-0 = <&mdss_dsi_active>;
    pinctrl-1 = <&mdss_dsi_suspend>;

    qcom,platform-reset-gpio = <&tlmm 60 0>;      // rst
    qcom,platform-enable-gpio= <&tlmm 46 0>;    //供电引脚
};

            //(mdss_dsi.c)   disp_en_gpio bklt_en_gpio rst_gpio
           // mdss_dsi_parse_gpio_params 
                 ctrl_pdata->disp_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,"qcom,platform-enable-gpio", 0);
            ctrl_pdata->disp_te_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,"qcom,platform-te-gpio", 0);
            ctrl_pdata->bklt_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,"qcom,platform-bklight-en-gpio", 0);
            ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,"qcom,platform-reset-gpio", 0);
                ctrl_pdata->mode_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,"qcom,platform-mode-gpio", 0);

           // mdss_dsi_panel_power_on
                    mdss_dsi_panel_reset(pdata, 1);   // (mdss_dsi_panel.c)
                        gpio_set_value((ctrl_pdata->bklt_en_gpio), 0);
            gpio_set_value((ctrl_pdata->disp_en_gpio), 0);
                gpio_set_value((ctrl_pdata->rst_gpio), 0);


           // mdss_dsi_panel_power_off
                   mdss_dsi_panel_reset(pdata, 0); // (mdss_dsi_panel.c)
            gpio_set_value((ctrl_pdata->bklt_en_gpio), 0);
            gpio_set_value((ctrl_pdata->disp_en_gpio), 0);
                gpio_set_value((ctrl_pdata->rst_gpio), 0);


// (msm8917-pinctrl.dtsi)

pmx_mdss: pmx_mdss {
            mdss_dsi_active: mdss_dsi_active {
                mux {
                    pins = "gpio60", "gpio46";
                    function = "gpio";
                };

                config {
                    pins = "gpio60", "gpio46";
                    drive-strength = <8>; /* 8 mA */
                    bias-disable = <0>; /* no pull */
//                  output-high;
                };
            };
            mdss_dsi_suspend: mdss_dsi_suspend {
                mux {
                    pins = "gpio60", "gpio46";
                    function = "gpio";
                };

                config {
                    pins = "gpio60", "gpio46";
                    drive-strength = <2>; /* 2 mA */
                    bias-pull-down; /* pull down */
                };
            };
 
10.esd功能
qcom,esd-check-enabled                      // 是否使用esd check 功能
qcom,mdss-dsi-panel-status-check-mode       // esd check的方式 te_signal_check (只能在cmd模式下用)or reg_read
 
10.1 cmd mode demo
qcom,mdss-dsi-te-pin-select = <1>;
        qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line = <0x2c>;
        qcom,mdss-dsi-te-v-sync-continue-lines = <0x3c>;
        qcom,mdss-dsi-te-dcs-command = <1>;
        qcom,esd-check-enabled;                                         // enable esd check
        qcom,mdss-dsi-panel-status-check-mode = "te_signal_check";              // esd check mode   te模式 (只能用作cmd模式)
        qcom,mdss-dsi-te-check-enable;                                      // te
        qcom,mdss-dsi-te-using-te-pin;                                      // use te pin   
 
10.2 video mode demo

qcom,esd-check-enabled;
        qcom,mdss-dsi-panel-status-check-mode = "reg_read";
        qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08];
        qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
        qcom,mdss-dsi-panel-status-read-length = <1>;
        qcom,mdss-dsi-panel-max-error-count = <2>;
        qcom,mdss-dsi-panel-status-value = <0x9c>;
 

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#include <dt-bindings/interrupt-controller/arm-gic.h> 2 3 &soc { 4 mdss_mdp: qcom,mdss_mdp@5e00000 { 5 compatible = "qcom,sde-kms"; 6 reg = <0x05e00000 0x8f030>, 7 <0x05eb0000 0x2008>, 8 <0x05e8f000 0x030>; 9 reg-names = "mdp_phys", 10 "vbif_phys", 11 "sid_phys"; 12 13 /* interrupt config */ 14 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 15 interrupt-controller; 16 #interrupt-cells = <1>; 17 18 /* Enable thermal cooling device */ 19 #cooling-cells = <2>; 20 21 /* hw blocks */ 22 qcom,sde-off = <0x1000>; 23 qcom,sde-len = <0x494>; 24 25 qcom,sde-ctl-off = <0x2000>; 26 qcom,sde-ctl-size = <0x1dc>; 27 qcom,sde-ctl-display-pref = "primary"; 28 29 qcom,sde-mixer-off = <0x45000>; 30 qcom,sde-mixer-size = <0x320>; 31 qcom,sde-mixer-display-pref = "primary"; 32 33 qcom,sde-dspp-top-off = <0x1300>; 34 qcom,sde-dspp-top-size = <0x80>; 35 qcom,sde-dspp-off = <0x55000>; 36 qcom,sde-dspp-size = <0x1800>; 37 38 qcom,sde-dspp-rc-version = <0x00010000>; 39 qcom,sde-dspp-rc-off = <0x15800>; 40 qcom,sde-dspp-rc-size = <0x100>; 41 qcom,sde-dspp-rc-mem-size = <2720>; 42 qcom,sde-dspp-rc-min-region-width = <4>; 43 44 qcom,sde-intf-off = <0x0 0x6b800>; 45 qcom,sde-intf-size = <0x2c0>; 46 qcom,sde-intf-type = "none", "dsi"; 47 qcom,sde-intf-tear-irq-off = <0 0x6e800>; 48 49 qcom,sde-pp-off = <0x71000>; 50 qcom,sde-pp-size = <0xd4>; 51 52 qcom,sde-dsc-off = <0x81000>; 53 qcom,sde-dsc-size = <0x140>; 54 qcom,sde-dsc-hw-rev = "dsc_1_1"; 55 56 qcom,sde-dither-off = <0x30e0>; 57 qcom,sde-dither-version = <0x00010000>; 58 qcom,sde-dither-size = <0x20>; 59 60 qcom,sde-sspp-type = "vig", "dma"; 61 62 qcom,sde-sspp-off = <0x5000 0x25000>; 63 qcom,sde-sspp-src-size = <0x1f8>; 64 65 qcom,sde-sspp-xin-id = <0 1>; 66 qcom,sde-sspp-excl-rect = <1 1>; 67 qcom,sde-sspp-smart-dma-priority = <2 1>; 68 qcom,sde-smart-dma-rev = "smart_dma_v2p5"; 69 70 qcom,sde-mixer-pair-mask = <0>; 71 qcom,sde-mixer-stage-base-layer; 72 73 qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 74 0xb0 0xc8 0xe0 0xf8 0x110>; 75 76 qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>; 77 78 qcom,sde-max-per-pipe-bw-high-kbps = <4100000 4100000>; 79 80 /* offsets are relative to "mdp_phys + qcom,sde-off */ 81 qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>; 82 qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>; 83 qcom,sde-sspp-csc-off = <0x1a00>; 84 qcom,sde-csc-type = "csc-10bit"; 85 qcom,sde-qseed-sw-lib-rev = "qseedv3lite"; 86 qcom,sde-qseed-scalar-version = <0x3000>; 87 qcom,sde-sspp-qseed-off = <0xa00>; 88 qcom,sde-sspp-linewidth = <2160>; 89 qcom,sde-vig-sspp-linewidth = <4096>; 90 qcom,sde-scaling-linewidth = <2560>; 91 qcom,sde-mixer-linewidth = <2048>; 92 qcom,sde-mixer-blendstages = <0x4>; 93 qcom,sde-highest-bank-bit = <0x0 0x1>; 94 qcom,sde-ubwc-version = <0x20000000>; 95 qcom,sde-ubwc-swizzle = <0x6>; 96 qcom,sde-ubwc-bw-calc-version = <0x1>; 97 qcom,sde-ubwc-static = <0x1e>; 98 qcom,sde-macrotile-mode = <0x0>; 99 qcom,sde-panic-per-pipe; 100 qcom,sde-has-cdp; 101 qcom,sde-has-dim-layer; 102 qcom,sde-max-bw-low-kbps = <5200000>; 103 qcom,sde-max-bw-high-kbps = <6200000>; 104 qcom,sde-min-core-ib-kbps = <2500000>; 105 qcom,sde-min-llcc-ib-kbps = <0>; 106 qcom,sde-min-dram-ib-kbps = <1600000>; 107 qcom,sde-dram-channels = <1>; 108 qcom,sde-num-nrt-paths = <0>; 109 110 qcom,sde-vbif-off = <0>; 111 qcom,sde-vbif-size = <0x2008>; 112 qcom,sde-vbif-id = <0>; 113 qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; 114 qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; 115 116 qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6 3 3 4 4 5 5 6 6>; 117 qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3>; 118 119 qcom,sde-qos-refresh-rates = <60 120>; 120 qcom,sde-danger-lut = <0xffff 0xffff 0xffff 0xffff 0x0 0x0 0x0 0x0 0x0 121 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, 122 <0x3ffff 0x3ffff 0x3ffff 0x3ffff 0x0 0x0 0x0 0x0 0x0 123 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; 124 125 qcom,sde-safe-lut = <0xff00 0xff00 0xff00 0xff00 0xffff 0xffff 0x0 0x0 0x0 126 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>, 127 <0xfe00 0xfe00 0xfe00 0xfe00 0xffff 0xffff 0x0 0x0 0x0 128 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>; 129 130 qcom,sde-creq-lut = <0x00112233 0x44556677 0x00112233 0x66777777 131 0x00112233 0x44556677 0x00112233 0x66777777 132 0x0 0x0 0x0 0x0 133 0x0 0x0 0x0 0x0 134 0x0 0x0 0x0 0x0 135 0x0 0x0 0x0 0x0 136 0x0 0x0 0x0 0x0 137 0x0 0x0 0x0 0x0 138 0x0 0x0 0x0 0x0>, 139 <0x00112234 0x45566777 0x00112236 0x67777777 140 0x00112234 0x45566777 0x00112236 0x67777777 141 0x0 0x0 0x0 0x0 142 0x0 0x0 0x0 0x0 143 0x0 0x0 0x0 0x0 144 0x0 0x0 0x0 0x0 145 0x0 0x0 0x0 0x0 146 0x0 0x0 0x0 0x0 147 0x0 0x0 0x0 0x0>; 148 149 qcom,sde-cdp-setting = <1 1>, <1 0>; 150 151 qcom,sde-qos-cpu-mask = <0x3>; 152 qcom,sde-qos-cpu-mask-performance = <0x3f>; 153 qcom,sde-qos-cpu-dma-latency = <300>; 154 qcom,sde-qos-cpu-irq-latency = <300>; 155 156 qcom,sde-secure-sid-mask = <0x821>; 157 qcom,sde-num-mnoc-ports = <1>; 158 qcom,sde-axi-bus-width = <32>; 159 160 qcom,sde-reg-bus,vectors-KBps = <0 0>, 161 <0 76800>, 162 <0 150000>, 163 <0 300000>; 164 165 qcom,sde-sspp-vig-blocks { 166 qcom,sde-vig-csc-off = <0x1a00>; 167 qcom,sde-vig-qseed-off = <0xa00>; 168 qcom,sde-vig-qseed-size = <0xa0>; 169 }; 170 171 qcom,sde-dspp-blocks { 172 qcom,sde-dspp-igc = <0x0 0x00030001>; 173 qcom,sde-dspp-hsic = <0x800 0x00010007>; 174 qcom,sde-dspp-memcolor = <0x880 0x00010007>; 175 qcom,sde-dspp-hist = <0x800 0x00010007>; 176 qcom,sde-dspp-sixzone= <0x900 0x00010007>; 177 qcom,sde-dspp-vlut = <0xa00 0x00010008>; 178 qcom,sde-dspp-pcc = <0x1700 0x00040000>; 179 qcom,sde-dspp-gc = <0x17c0 0x00010008>; 180 qcom,sde-dspp-dither = <0x82c 0x00010007>; 181 }; 182 183 }; 184 185 mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { 186 compatible = "qcom,dsi-ctrl-hw-v2.4"; 187 label = "dsi-ctrl-0"; 188 cell-index = <0>; 189 frame-threshold-time-us = <1000>; 190 reg = <0x05e94000 0x400>, 191 <0x05f08000 0x4>, 192 <0x05e6b800 0x300>; 193 reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base"; 194 interrupt-parent = <&mdss_mdp>; 195 interrupts = <4 0>; 196 197 qcom,ctrl-supply-entries { 198 #address-cells = <1>; 199 #size-cells = <0>; 200 201 qcom,ctrl-supply-entry@0 { 202 reg = <0>; 203 qcom,supply-name = "vdda-1p2"; 204 qcom,supply-min-voltage = <1200000>; 205 qcom,supply-max-voltage = <1200000>; 206 qcom,supply-enable-load = <21800>; 207 qcom,supply-disable-load = <0>; 208 }; 209 }; 210 211 qcom,core-supply-entries { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 215 qcom,core-supply-entry@0 { 216 reg = <0>; 217 qcom,supply-name = "refgen"; 218 qcom,supply-min-voltage = <0>; 219 qcom,supply-max-voltage = <0>; 220 qcom,supply-enable-load = <0>; 221 qcom,supply-disable-load = <0>; 222 }; 223 }; 224 }; 225 226 mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94900 { 227 compatible = "qcom,dsi-phy-v4.1"; 228 label = "dsi-phy-0"; 229 cell-index = <0>; 230 #clock-cells = <1>; 231 reg = <0x05e94400 0x800>, 232 <0x05e94900 0x264>, 233 <0x05f01004 0x8>, 234 <0x05e94200 0x100>; 235 reg-names = "dsi_phy", "pll_base", "gdsc_base", "dyn_refresh_base"; 236 pll-label = "dsi_pll_5nm"; 237 238 qcom,platform-strength-ctrl = [55 03 239 55 03 240 55 03 241 55 03 242 55 00]; 243 qcom,platform-lane-config = [00 00 0a 0a 244 00 00 0a 0a 245 00 00 0a 0a 246 00 00 0a 0a 247 00 00 8a 8a]; 248 qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; 249 qcom,phy-supply-entries { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 qcom,phy-supply-entry@0 { 253 reg = <0>; 254 qcom,supply-name = "vdda-0p9"; 255 qcom,supply-min-voltage = 256 <RPMH_REGULATOR_LEVEL_SVS_L1>; 257 qcom,supply-max-voltage = 258 <RPMH_REGULATOR_LEVEL_TURBO_L1>; 259 qcom,supply-off-min-voltage = 260 <RPMH_REGULATOR_LEVEL_RETENTION>; 261 qcom,supply-enable-load = <0>; 262 qcom,supply-disable-load = <0>; 263 }; 264 }; 265 }; 266 };
最新发布
09-19
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