Transfer IDs

The AXI protocol defines an ID signals bus for each channel. Marking each transaction with an
ID gives the possibility to complete transactions out of order. This means that transactions to
faster memory regions can complete without waiting for earlier transactions to slower memory
regions. The use of transfer IDs enables the implementation of a high-performance interconnect,
maximizing data throughput and system efficiency. This feature can also improve system
performance because it reduces the effect of transaction latency.

The ID signal buses are as follows:
• AWID
• WID
• BID
• ARID
• RID
The AXI protocol supports out-of-order transactions by enabling each interface to act as multiple
ordered interfaces. According to the AXI protocol specifications, all transactions with a given ID
must be ordered. However, there is no restriction on the ordering of transactions with different IDs.
同ID保序，不同ID乱序
When working with transfer IDs, follow these rules:
• All transfers must have an ID.
• All transfers in a transaction must have the same ID.
• Managers can support multiple IDs for multiple threads.
• Subordinates generally need a configurable ID width.
You should also remember these two important AXI parameters for ID signals:
• The write ID width, which is the number of bits used for the AWID, WID and BID buses
• The read ID width, which is the number of bits used for the ARID and RID buses