Clarification for SMS Wrapper synthesis and STA timing exceptions

1. This section contains the explanation of the timing exceptions for sn6xx000vpnnsmwrp000sa18 SMS Wrapper.

Compared with SMS 5.x, where data exchange between fast and slow clock domains happens, in SMS 6x, due to the clock switching mechanism, communicating components of the system (during data exchange)  are clocked by the same clock signal. The logic that implements clock switching is called glitch free clock switching mechanism and is shown below (Figure 1): 

Figure 1   

As shown in above figure, the clock_out will be either a fast clock, or a slow clock. So there is no need of synchronization between the clocks. 
In  SMS 6.x we have the mentioned exceptions:
set_false_path -from [get_clocks {*clkgrp_mem*}]   -to [get_clocks {*clkgrp_bist*}]
set_false_path -from [get_clocks {*clkgrp_bist*}]  -to [get_clocks {*clkgrp_mem*}]
Taking in to account that the memory is either in BIST mode or in functional mode, so the following paths can be considered as a false paths.

set_false_path -through [get_cells -quiet -hier -f {full_name =~ *dwsms_fp_buf*}]
This path is connected to memory BISTE/TCLKE signal in the SMS design. BISTE signal is toggling only when ME is inactive,so the timing to BISTE/TCLKE is not real.

set_false_path -through [get_cells -quiet -hier -f {full_name =~ *dwsms_slow_buf*}] -to [get_clocks {*clkgrp_bist*}]
set_false_path -from [get_clocks {*clkgrp_bist*}] -through [get_cells -quiet -hier -f {full_name =~ *dwsms_slow_buf*}]
Due to the absence of data exchange between clock domains the mentioned paths are considered as a false paths.

set_multicycle_path 4 -setup -from [get_ports rst_sms]
set_multicycle_path 7 -hold  -from [get_ports rst_sms]
There is a requirement that tclk_sms should be activated after the 2 WRCK cycles when rst_sms is high. Because of the glitch free clock switching mechanism tclk_sms is activated after additional 2 WRCK cycles. This is the reason that setup requirement is 4. The requirement for hold time is 4 plus the additional 3(at least) WRCK cycles for rst_sms to be Low.

 
2. This section contains the explanation of the timing exceptions for vl50x000vpnnsmwrp000sa34p4 SMS Wrapper.
Depending on memory and Wrapper configurations the specific timing exception listed below
(in bold) may or may not be in the SDC file. The intend of this article is just to give an idea
why the specific signal has been constrained this way.

a) set_max_delay  [expr 1 * $T_bist] -from [filter_collection $MBIST_all_seq_cells {full_name =~ *U_wrap_sctrl*half_wrck* }] -to [get_clocks {clkgrp_bist}] 
One clk_sms cycle is considered here in order to be able to relax the budget needed for capturing the data from fast to slow domain(2 clk_sms cycle, refer to constraint (d)). Shown in Figure 2.

b) set_max_delay  [expr 3 * $T_bist] -from [filter_collection $MBIST_all_seq_cells {full_name =~ *U_wrap_sctrl*wr_se_r* }]   -to [get_clocks {clkgrp_bist}]
The pulse that enables wr_se_r signal capturing, takes 3 clk_sms cycles to be formed(because of 3 stage synchronizer). Shown in Figure 2.

c) set_max_delay  [expr 4 * $T_bist] -from [get_clocks {clkgrpslow}]   -to [get_clocks {clkgrp_bist}]
set_false_path -hold -from [get_clocks {clkgrp_bist}]   -to [get_clocks {clkgrpslow}]
Plus extra 1 cycle(4 clk_sms) is needed to form a pulse(status_se...) enabling the mux which should capture the scan input.
Hold does not need to be checked since the WSI data is at least 8 times slower than the status_se pulse and therefore limited by status_se. Meeting the setup time requirement, WSI data will be always static at the time status_se goes low.
Shown in Figure 2.

d) set_max_delay  [expr $T_slow - (6 * $T_bist)] -from [get_clocks {clkgrp_bist}]   -to [get_clocks {clkgrpslow}]
set_false_path -hold -from [get_clocks {clkgrp_bist}]   -to [get_clocks {clkgrpslow}]
Assuming that the data  path from slow to fast can be delayed by 4 clk_sms cycles(constraint (c)) and plus 1 extra cycle from half_wrck_r to the synchronyzer first flop (constraint (a)), the budget left to transfer the data from slow to fast have a budget of 2 clk_sms cycles(calculation has done with ratio 8:1, and assuming clocks are asynchron). Hold does not need to be checked since the WSOR data is at least 8 times slower than the status_se pulse and therefore limited by status_se. Meeting the setup time requirement, WSI data will be always static at the time status_se goes low. Shown in Figure 2.

Figure 2

set_false_path -from [get_clocks {clkgrpslow}]   -to [filter_collection $MBIST_all_seq_cells {full_name =~ *_met*f_sel_chain_r*}]
f_sel_chain_r is fast clk_sms clock driven register originated from slow sel_chain_r driven by slow WRCK clock.
sel_chain_r will be changed when the SMS instruction is changed. The f_sel_chain_r signal is used to select the proper registers chain depending on instruction selected. There is a huge number of WRCK clock cycles between loading the instruction register and operation with the data register. This is due to JTAG state machine which needs several clock cycles to activate data registers. It is not realistic to delay the path from sel_chain_r to f_sel_chain_r for such slow clock cycles.

set_false_path -from [get_clocks {clkgrpslow}]   -to [filter_collection $MBIST_all_seq_cells {full_name =~ *dwsms_*_met_signal_r*0* && full_name !~ *dwsms_*ticker*}]
This goes to BISTE/TCLKE signal in the SMS design. BISTE signal is toggling only when ME is inactive, so the timing to BISTE/TCLKE is not real.

set_false_path -from [get_clocks {clkgrpslow}]   -to [get_clocks {clkgrp_mem}]
set_false_path -from [get_clocks {clkgrp_mem}]   -to [get_clocks {clkgrpslow}]

set_false_path -from [get_clocks {clkgrp_mem}]   -to [get_clocks {clkgrp_bist}]
set_false_path -from [get_clocks {clkgrp_bist}]   -to [get_clocks {clkgrp_mem}]
Taking in to account that the memory is either in BIST mode or in functional mode, so the following paths are considered as a false paths.

set_false_path -from [get_ports rst_sms]
When reset_type = 0 or 1 the synchronizers are being added on this path
When reset_type = 2 there are requirement to keep clocks inactive.
Hence this path are considered as a false path.

set_false_path -from [get_ports dm2]
set_false_path -from [get_ports dm1]
set_false_path -from [get_ports dm0]
The dm pins are static during the BIST mode so this paths are considered as a false paths.

set_false_path -from [filter_collection $MBIST_all_seq_cells {full_name =~ *biste*dwsms_*_met_signal_r*2*}] -through $MEM_all_pins
This path is connected to memory BISTE/TCLKE signal in the SMS design. BISTE signal is toggling only when ME is inactive, so the timing to BISTE/TCLKE is not real.