preloader

原创已于 2025-08-22 09:06:29 修改 · 700 阅读

19 ·

CC 4.0 BY-SA版权

文章标签：

#android

于 2025-07-29 08:21:25 首次发布

Android 专栏收录该内容

25 篇文章

订阅专栏

patch

调试串口115200

--- a/platform/ac8257/default.mak
+++ b/platform/ac8257/default.mak
@@ -40,7 +40,7 @@ CFG_USB_DOWNLOAD :=1
 CFG_FUNCTION_PICACHU_SUPPORT :=1
 CFG_PMT_SUPPORT :=0
 CFG_UART_COMMON :=1
-CFG_LOG_BAUDRATE :=921600
+CFG_LOG_BAUDRATE :=115200
 CFG_EVB_UART_CLOCK :=26000000
 CFG_FPGA_UART_CLOCK :=12000000
 CFG_META_BAUDRATE :=115200
@@ -111,7 +111,7 @@ CFG_PMIC_FULL_RESET :=0
 
 # dynamic switch UART log and profile boot time in user load
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-	CFG_UART_DYNAMIC_SWITCH :=1
+	CFG_UART_DYNAMIC_SWITCH :=0
 	CFG_BOOT_TIME_PROFILE :=0
 else
 	CFG_UART_DYNAMIC_SWITCH :=0

GPIO

--- a/platform/ac8257/src/core/load_arm2_image.c
+++ b/platform/ac8257/src/core/load_arm2_image.c
@@ -851,6 +851,11 @@ static void preloader_setup_display_gpio(void)
 	mt_set_gpio_out (GPIO159, GPIO_OUT_ZERO);
     //mt_set_gpio_pull_select(GPIO159, GPIO_PULL_DOWN);
 #else
+	/* 5V */
+	mt_set_gpio_mode(GPIO16, GPIO_MODE_00);
+	mt_set_gpio_dir (GPIO16, GPIO_DIR_OUT);
+	mt_set_gpio_out (GPIO16, GPIO_OUT_ONE);
+
+	/* 12V */
+	mt_set_gpio_mode(GPIO175, GPIO_MODE_GPIO);
+	mt_set_gpio_dir(GPIO175,GPIO_DIR_OUT);
+	mt_set_gpio_out(GPIO175, GPIO_OUT_ONE);
+
+	/* 12V */
+	mt_set_gpio_mode(GPIO167, GPIO_MODE_GPIO);
+	mt_set_gpio_dir(GPIO167,GPIO_DIR_OUT);
+	mt_set_gpio_out(GPIO167, GPIO_OUT_ONE);

 	mt_set_gpio_mode(GPIO151, GPIO_MODE_00);
 	mt_set_gpio_dir (GPIO151, GPIO_DIR_OUT);
 	mt_set_gpio_out (GPIO151, GPIO_OUT_ONE);

watchdog

--- a/platform/ac8257/default.mak
+++ b/platform/ac8257/default.mak
@@ -80,7 +80,7 @@ CFG_APWDT :=V2
 #   0       : Disable watchdog
 #   1       : Enable watchdog
 #
-CFG_APWDT_DISABLE :=0
+CFG_APWDT_DISABLE :=1
 CFG_BOOT_ARGUMENT :=1
 CFG_BOOT_ARGUMENT_BY_ATAG := 1
 CFG_RAM_CONSOLE :=1
@@ -135,7 +135,7 @@ endif
 # LOG_LEVEL_DEBUG      (4)
 # Any log messages with levels less than and equal to this will be printed.
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-CFG_LOG_LEVEL :=0
+CFG_LOG_LEVEL :=3
 else
 CFG_LOG_LEVEL :=0
 endif
--- a/platform/ac8257/src/core/main.c
+++ b/platform/ac8257/src/core/main.c
@@ -1385,6 +1385,11 @@ void main(u32 *arg)
     jump_arg = (u32)&bootarg;
 #endif
 
+	for (;;) {
+		if (get_timer(0) > 120000) {
+			break;
+		}
+	}
     /* 64S3,32S1,32S1 (MTK_ATF_BOOT_OPTION = 0)
 	 * re-loader jump to LK directly and then LK jump to kernel directly */
 #if CFG_ATF_SUPPORT

UART DYNAMIC SWITCH

--- a/platform/ac8257/src/drivers/platform.c
+++ b/platform/ac8257/src/drivers/platform.c
@@ -1498,7 +1498,7 @@ void platform_init(void)
         pal_log_info("Vol Up detected. Log Keep on.\n");
     } else {
         pal_log_err("Log Turned Off.\n");
-        set_log_switch(0);
+        //set_log_switch(0);
     }
     BOOTING_TIME_PROFILING_LOG("UART DYNAMIC SWITCH");
 #endif

gpt debug

--- a/platform/ac8257/default.mak
+++ b/platform/ac8257/default.mak
@@ -135,7 +135,7 @@ endif
 # LOG_LEVEL_DEBUG      (4)
 # Any log messages with levels less than and equal to this will be printed.
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-CFG_LOG_LEVEL :=0
+CFG_LOG_LEVEL :=4
 else
 CFG_LOG_LEVEL :=0
 endif
--- a/platform/ac8257/src/drivers/platform.c
+++ b/platform/ac8257/src/drivers/platform.c
@@ -1498,7 +1498,7 @@ void platform_init(void)
         pal_log_info("Vol Up detected. Log Keep on.\n");
     } else {
         pal_log_err("Log Turned Off.\n");
-        set_log_switch(0);
+        //set_log_switch(0);
     }
     BOOTING_TIME_PROFILING_LOG("UART DYNAMIC SWITCH");
 #endif
--- a/platform/common/partition/efi.c
+++ b/platform/common/partition/efi.c
@@ -189,7 +189,7 @@ static int read_data(u8 *buf, u32 part_id, u64 lba, u64 size)
 
     err = blkdev_read(dev, lba * dev->blksz, (u32)size, buf, part_id);
     if (err) {
-        pal_log_err("%sread data, err(%d)\n", TAG, err);
+        pal_log_err("%sread data lba 0x%llx, err(%d)\n", TAG, lba, err);
         return err;
     }
 
@@ -252,8 +252,13 @@ static u64 get_part_ptr_by_gpt(u32 part_id, u64 header_lba, u8 *entries_buf, par
         return 1;
     }
 
+    if (header->sizeof_partition_entry < sizeof(gpt_entry)) {
+        pal_log_err("%s invalid sizeof_partition_entry 0x%llx, default sizeof(gpt_entry)\n", TAG, header->sizeof_partition_entry);
+        header->sizeof_partition_entry = sizeof(gpt_entry);
+    }
     num_block_entry = (u64)(blksz / header->sizeof_partition_entry);
     entries_read_size = (u64)((header->num_partition_entries + (num_block_entry - 1)) / num_block_entry) * blksz;
+    pal_log_info("%s num_block_entry 0x%llx, entries_read_size 0x%llx\n", TAG, num_block_entry, entries_read_size);
 
     calc_crc = ~0L;
     read_lba = header->partition_entry_lba;
@@ -276,11 +281,15 @@ static u64 get_part_ptr_by_gpt(u32 part_id, u64 header_lba, u8 *entries_buf, par
     }
     calc_crc = efi_crc32_finalize(calc_crc);
     if (header->partition_entry_array_crc32 != calc_crc) {
-        pal_log_err("%scheck header, err(entries crc 0x%x!=0x%x(calc))\n",
-            TAG, header->partition_entry_array_crc32, calc_crc);
+        pal_log_err("%scheck header, err(entries crc 0x%x!=0x%x(calc)) 0x%llx\n",
+            TAG, header->partition_entry_array_crc32, calc_crc, header_lba);
         memset(part_ptr, 0, sizeof(part_t));
         return 1;
     }
+
+    pal_log_err("%scheck header, err(entries crc 0x%x 0x%x(calc)) 0x%llx\n",
+        TAG, header->partition_entry_array_crc32, calc_crc, header_lba);
+
     if (found == 0)
         memset(part_ptr, 0, sizeof(part_t));
 
@@ -304,6 +313,7 @@ int mt_get_part_info_by_name(const char *name, struct part_info_t *part_info)
     }
     gpt_sram_part_info.info = &gpt_sram_part_meta_info;
     if (get_part_ptr_by_gpt(part_id, 1, gpt_sram_buf, &gpt_sram_part_info, name, dev->blksz) != 0) {
+        gpt_sram_part_info.info = &gpt_sram_part_meta_info;
         if (get_part_ptr_by_gpt(part_id, last_lba(part_id), gpt_sram_buf, &gpt_sram_part_info, name, dev->blksz) != 0) {
             pal_log_err("%sFailure to find valid GPT.\n", TAG);
             return 1;
@@ -317,10 +327,12 @@ int mt_get_part_info_by_name(const char *name, struct part_info_t *part_info)
 u64 get_part_addr(const char *name) {
     struct part_info_t part_info;
 
+    pal_log_err("%sget_part_addr %s\n", TAG, name);
     if (mt_get_part_info_by_name(name, &part_info) != 0) {
         pal_log_err("%smt_get_part_info_by_name fail\n", TAG);
         return 0;
     } else {
+        pal_log_err("%sget_part_addr %s: 0x%llx\n", TAG, name, (u64)part_info.addr);
         return (u64)part_info.addr;
     }
 }
--- a/platform/common/partition/part_common.c
+++ b/platform/common/partition/part_common.c
@@ -45,6 +45,7 @@
 #include <bootctrl.h>
 #include <platform.h>
 
+#define MOD     "[PART]"
 #ifdef MTK_PARTITION_COMMON
 #include "dram_buffer.h"
 #include "partition.h"
--- a/platform/common/storage/mmc/msdc_dma.c
+++ b/platform/common/storage/mmc/msdc_dma.c
@@ -949,7 +949,7 @@ done:
 	if (derr != MMC_ERR_NONE) {
 		/* crc error find in data transfer. need reset host & send cmd12 */
 		/* if autocmd crc occur, will enter here too */
-		msdc_pr_err("[SD%d] <CMD%d> DMA data error (%d)\n", host->id, cmd->opcode, derr);
+		msdc_pr_err("[SD%d] <CMD%d> 0x%x DMA data error (%d)\n", host->id, cmd->opcode, cmd->arg, derr);
 		msdc_abort_handler(host, 1);
 
 		return derr;

parition

--- a/platform/common/partition/efi.c
+++ b/platform/common/partition/efi.c
@@ -252,6 +252,10 @@ static u64 get_part_ptr_by_gpt(u32 part_id, u64 header_lba, u8 *entries_buf, par
         return 1;
     }
 
+    if (header->sizeof_partition_entry < sizeof(gpt_entry)) {
+        header->sizeof_partition_entry = sizeof(gpt_entry);
+    }
+
     num_block_entry = (u64)(blksz / header->sizeof_partition_entry);
     entries_read_size = (u64)((header->num_partition_entries + (num_block_entry - 1)) / num_block_entry) * blksz;
 
@@ -260,6 +264,9 @@ static u64 get_part_ptr_by_gpt(u32 part_id, u64 header_lba, u8 *entries_buf, par
     found = 0;
     while (entries_read_size > 0) {
         err = read_data((u8*)entries_buf, part_id, read_lba, GPT_SRAM_BUF_SIZE);
+        if (err) {
+            break;
+        }
         read_lba = read_lba + GPT_SRAM_BUF_SIZE/blksz;
         calc_crc = efi_crc32(calc_crc, (u8 *)entries_buf, (u32)GPT_SRAM_BUF_SIZE, gpt_sram_crc32_table);
         entries_read_size -= GPT_SRAM_BUF_SIZE;
@@ -304,6 +311,7 @@ int mt_get_part_info_by_name(const char *name, struct part_info_t *part_info)
     }
     gpt_sram_part_info.info = &gpt_sram_part_meta_info;
     if (get_part_ptr_by_gpt(part_id, 1, gpt_sram_buf, &gpt_sram_part_info, name, dev->blksz) != 0) {
+        gpt_sram_part_info.info = &gpt_sram_part_meta_info;
         if (get_part_ptr_by_gpt(part_id, last_lba(part_id), gpt_sram_buf, &gpt_sram_part_info, name, dev->blksz) != 0) {
             pal_log_err("%sFailure to find valid GPT.\n", TAG);
             return 1;
@@ -349,6 +357,11 @@ static int parse_gpt_header(u32 part_id, u64 header_lba, u8 *header_buf, u8 *ent
         return 1;
     }
 
+    if (header->sizeof_partition_entry != sizeof(gpt_entry)) {
+        pal_log_err("%sinvalid sizeof_partition_entry %d, default to %d\n",
+            TAG, header->sizeof_partition_entry, sizeof(gpt_entry));
+        header->sizeof_partition_entry = sizeof(gpt_entry);
+    }
     entries_real_size = (u64)header->num_partition_entries * header->sizeof_partition_entry;
     num_block_entry = (u64)(dev->blksz / header->sizeof_partition_entry);
     entries_read_size = (u64)((header->num_partition_entries + (num_block_entry - 1)) / num_block_entry) * dev->blksz;

boot time profile

--- a/platform/ac8257/default.mak
+++ b/platform/ac8257/default.mak
@@ -112,7 +112,7 @@ CFG_PMIC_FULL_RESET :=0
 # dynamic switch UART log and profile boot time in user load
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
 	CFG_UART_DYNAMIC_SWITCH :=1
-	CFG_BOOT_TIME_PROFILE :=0
+	CFG_BOOT_TIME_PROFILE :=1
 else
 	CFG_UART_DYNAMIC_SWITCH :=0
 	CFG_BOOT_TIME_PROFILE :=0
@@ -135,7 +135,7 @@ endif
 # LOG_LEVEL_DEBUG      (4)
 # Any log messages with levels less than and equal to this will be printed.
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-CFG_LOG_LEVEL :=0
+CFG_LOG_LEVEL :=2
 else
 CFG_LOG_LEVEL :=0
 endif
--- a/platform/ac8257/src/core/print.c
+++ b/platform/ac8257/src/core/print.c
@@ -198,6 +198,10 @@ void vprint(char *fmt, va_list vl)
     unsigned char c;
     unsigned int reg = 1; /* argument register number (32-bit) */
 
+    outchar('[');
+    outdec(get_timer(0));
+    outstr("] ");
+
     while (*fmt) {
         c = *fmt++;
         switch (c)

SBOOT ENABLE

--- a/custom/ac8257_car/ac8257_car.mk
+++ b/custom/ac8257_car/ac8257_car.mk
@@ -3,8 +3,8 @@ TARGET=ac8257_car
 ARM2_PROJECT=ac8257_car
 MTK_PLATFORM=AC8257
 MTK_SEC_CHIP_SUPPORT=yes
-MTK_SEC_USBDL=ATTR_SUSBDL_DISABLE
-MTK_SEC_BOOT=ATTR_SBOOT_DISABLE
+MTK_SEC_USBDL=ATTR_SUSBDL_ENABLE
+MTK_SEC_BOOT=ATTR_SBOOT_ENABLE
 MTK_SEC_MODEM_AUTH=no
 MTK_SEC_SECRO_AC_SUPPORT=yes
 # Platform
--- a/custom/ac8257_demo/ac8257_demo.mk
+++ b/custom/ac8257_demo/ac8257_demo.mk
@@ -3,8 +3,8 @@ TARGET=ac8257_demo
 ARM2_PROJECT=ac8257_demo
 MTK_PLATFORM=AC8257
 MTK_SEC_CHIP_SUPPORT=yes
-MTK_SEC_USBDL=ATTR_SUSBDL_DISABLE
-MTK_SEC_BOOT=ATTR_SBOOT_DISABLE
+MTK_SEC_USBDL=ATTR_SUSBDL_ENABLE
+MTK_SEC_BOOT=ATTR_SBOOT_ENABLE
 MTK_SEC_MODEM_AUTH=no
 MTK_SEC_SECRO_AC_SUPPORT=yes
 # Platform
--- a/custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk
+++ b/custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk
@@ -3,8 +3,8 @@ TARGET=ac8257_demo_1g_32
 ARM2_PROJECT=ac8257_demo_1g_32
 MTK_PLATFORM=AC8257
 MTK_SEC_CHIP_SUPPORT=yes
-MTK_SEC_USBDL=ATTR_SUSBDL_DISABLE
-MTK_SEC_BOOT=ATTR_SBOOT_DISABLE
+MTK_SEC_USBDL=ATTR_SUSBDL_ENABLE
+MTK_SEC_BOOT=ATTR_SBOOT_ENABLE
 MTK_SEC_MODEM_AUTH=no
 MTK_SEC_SECRO_AC_SUPPORT=yes
 # Platform

usbdl_verify_da

--- a/platform/ac8257/src/core/download.c
+++ b/platform/ac8257/src/core/download.c
@@ -472,6 +472,8 @@ static u16 usbdl_verify_da(u8* da_addr, u32 da_len, u32 sig_len)
 	if (FALSE == seclib_sec_usbdl_enabled(TRUE)) {
 		pal_log_info("usbdl_vfy_da:disabled\n");
 	} else {
+		status = 0;
+#if 0
 		/* init download agent authentication key */
 		if (da_auth_init() != 0) {
 			status = E_DAA_SIG_VERIFY_FAILED;
@@ -490,6 +492,7 @@ static u16 usbdl_verify_da(u8* da_addr, u32 da_len, u32 sig_len)
 		if (sec_auth(da_addr, (da_len - sig_len), sig_addr, sig_len) != 0) {
 			status = E_DAA_SIG_VERIFY_FAILED;
 		}
+#endif
 	}
 #else
 	if (FALSE == seclib_sec_usbdl_enabled(TRUE)) {

SBOOT ENABLE_ON_SCHIP

--- a/custom/ac8257_car/ac8257_car.mk
+++ b/custom/ac8257_car/ac8257_car.mk
@@ -3,8 +3,8 @@ TARGET=ac8257_car
 ARM2_PROJECT=ac8257_car
 MTK_PLATFORM=AC8257
 MTK_SEC_CHIP_SUPPORT=yes
-MTK_SEC_USBDL=ATTR_SUSBDL_DISABLE
-MTK_SEC_BOOT=ATTR_SBOOT_DISABLE
+MTK_SEC_USBDL=ATTR_SUSBDL_ONLY_ENABLE_ON_SCHIP
+MTK_SEC_BOOT=ATTR_SBOOT_ONLY_ENABLE_ON_SCHIP
 MTK_SEC_MODEM_AUTH=no
 MTK_SEC_SECRO_AC_SUPPORT=yes
 # Platform
--- a/custom/ac8257_demo/ac8257_demo.mk
+++ b/custom/ac8257_demo/ac8257_demo.mk
@@ -3,8 +3,8 @@ TARGET=ac8257_demo
 ARM2_PROJECT=ac8257_demo
 MTK_PLATFORM=AC8257
 MTK_SEC_CHIP_SUPPORT=yes
-MTK_SEC_USBDL=ATTR_SUSBDL_DISABLE
-MTK_SEC_BOOT=ATTR_SBOOT_DISABLE
+MTK_SEC_USBDL=ATTR_SUSBDL_ONLY_ENABLE_ON_SCHIP
+MTK_SEC_BOOT=ATTR_SBOOT_ONLY_ENABLE_ON_SCHIP
 MTK_SEC_MODEM_AUTH=no
 MTK_SEC_SECRO_AC_SUPPORT=yes
 # Platform
--- a/custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk
+++ b/custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk
@@ -3,8 +3,8 @@ TARGET=ac8257_demo_1g_32
 ARM2_PROJECT=ac8257_demo_1g_32
 MTK_PLATFORM=AC8257
 MTK_SEC_CHIP_SUPPORT=yes
-MTK_SEC_USBDL=ATTR_SUSBDL_DISABLE
-MTK_SEC_BOOT=ATTR_SBOOT_DISABLE
+MTK_SEC_USBDL=ATTR_SUSBDL_ONLY_ENABLE_ON_SCHIP
+MTK_SEC_BOOT=ATTR_SBOOT_ONLY_ENABLE_ON_SCHIP
 MTK_SEC_MODEM_AUTH=no
 MTK_SEC_SECRO_AC_SUPPORT=yes
 # Platform

memory test

--- a/platform/ac8257/src/drivers/dramc_pi_main.c
+++ b/platform/ac8257/src/drivers/dramc_pi_main.c
@@ -114,8 +114,8 @@
 #endif
 
 DRAM_DFS_FREQUENCY_TABLE_T gFreqTbl[DRAM_DFS_SHUFFLE_MAX] = {
-    {LP4_HIGHEST_FREQSEL, LP4_HIGHEST_FREQ, DRAM_DFS_SHUFFLE_1},
-    {LP4_MIDDLE_FREQSEL, LP4_MIDDLE_FREQ, DRAM_DFS_SHUFFLE_2},
+    {LP4_HIGHEST_FREQSEL, LP4_LOWEST_FREQ, DRAM_DFS_SHUFFLE_1},
+    {LP4_MIDDLE_FREQSEL, LP4_LOWEST_FREQ, DRAM_DFS_SHUFFLE_2},
     {LP4_LOWEST_FREQSEL,  LP4_LOWEST_FREQ, DRAM_DFS_SHUFFLE_3},
 };
 
--- a/platform/ac8257/src/drivers/memory.c
+++ b/platform/ac8257/src/drivers/memory.c
@@ -137,6 +137,7 @@ void mt_mem_init(void)
 #endif
 
 	/* CFG_UBOOT_MEMADDR is LK base addr */
+#if 0
 	if ((i = complex_mem_test(CFG_UBOOT_MEMADDR, MEM_TEST_SIZE)) == 0) {
 		print ("[%s] 1st complex R/W mem test pass (start addr:0x%x)\n", MOD, CFG_UBOOT_MEMADDR);
 	} else {
@@ -147,6 +148,16 @@ void mt_mem_init(void)
 		ASSERT(0);
 #endif
 	}
+#else
+	#define TEST_ADDR 0x40000000
+	#define TEST_SIZE CUSTOM_CONFIG_MAX_DRAM_SIZE	//3GB
+	if ((i = simple_mem_test(TEST_ADDR, TEST_SIZE)) == 0){
+		print("[%s] 1st simple R/W mem test pass (start addr:0x%X, size:0x%X)\n", MOD, TEST_ADDR, TEST_SIZE);
+	}else{
+		print("[%s] 1st simple R/W mem test fail :%X (start addr:0x%X, size:0x%X)\n", MOD, i, TEST_ADDR, TEST_SIZE);
+		ASSERT(0);
+	}
+#endif
 
 #if DUAL_RANK_ENABLE
 	if (get_dram_rank_nr() >= 2) {
@@ -200,22 +211,35 @@ void mt_mem_init(void)
 #define PATTERN1 0x5A5A5A5A
 #define PATTERN2 0xA5A5A5A5
 
+extern void mtk_wdt_disable(void);
+extern void mtk_wdt_enable(void);
+
 static int simple_mem_test(unsigned int start, unsigned int len)
 {
 	unsigned int *MEM32_BASE = (unsigned int *) start;
 	unsigned int i, orig_val, new_val;
 
+	mtk_wdt_disable();
+	print("simple mem test. start addr=0x%X, size=0x%X\n", start, len);
+
 	for (i = 0; i < (len >> 2); ++i) {
+		if((start+i*4) % 0xA00000 == 0){
+			print("simple mem test. addr=0x%X\n", start+i*4);
+		}
 		orig_val = MEM32_BASE[i];
 		dsb();
 		MEM32_BASE[i] = PATTERN1;
 		dsb();
 		new_val = MEM32_BASE[i];
-		if (new_val != PATTERN1)
+		if (new_val != PATTERN1){
+			print("simple mem test failed. addr=0x%X, value=0x%X\n", start+i*4, new_val);
+			mtk_wdt_enable();
 			return -1;
+		}
 		dsb();
 		MEM32_BASE[i] = orig_val;
 	}
+	mtk_wdt_enable();
 
 	return 0;
 }
--- a/platform/ac8257/src/drivers/pmic.c
+++ b/platform/ac8257/src/drivers/pmic.c
@@ -619,6 +619,7 @@ U32 pmic_init (void)
 	int ret_val = 0, val;
 
 	print("[PMIC]Preloader Start\n");
+	print("Mem test Preloader Start!\n");
 
 	print("[PMIC]AC8257 CHIP Code = 0x%x, mrv=%d\n"
 	      , get_PMIC_chip_version()

gpio dump

--- a/platform/ac8257/src/drivers/gpio.c
+++ b/platform/ac8257/src/drivers/gpio.c
@@ -886,11 +886,32 @@ S32 mt_get_gpio_drving(u32 pin)
 	return mt_get_gpio_driving_chip(pin);
 }
 #endif
+
+void gpio_dump(void)
+{
+	int i = 0;
+
+	print("gpio,mode,dir,pull_en,pull_sel,out,smt,ies,in\n");
+	for (i = 0; i < MAX_GPIO_PIN; i++) {
+		print("%d,%d,%d,%d,%d,%d,%d,%d,%d\n", i,
+			mt_get_gpio_mode(0x80000000 + i),
+			mt_get_gpio_dir(0x80000000 + i),
+			mt_get_gpio_pull_enable(0x80000000 + i),
+			mt_get_gpio_pull_select(0x80000000 + i),
+			mt_get_gpio_out(0x80000000 + i),
+			mt_get_gpio_smt(0x80000000 + i),
+			mt_get_gpio_ies(0x80000000 + i),
+			mt_get_gpio_in(0x80000000 + i));
+	}
+
+	print("\n");
+}
 /*****************************************************************************/
 /* sysfs operation                                                           */
 /*****************************************************************************/
 void mt_gpio_init(void)
 {
+	gpio_dump();
 #ifdef DUMMY_AP
 	mt_gpio_set_default();
 #endif

CFG_LOG_LEVEL 4

--- a/platform/ac8257/default.mak
+++ b/platform/ac8257/default.mak
@@ -111,8 +111,8 @@ CFG_PMIC_FULL_RESET :=0
 
 # dynamic switch UART log and profile boot time in user load
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-	CFG_UART_DYNAMIC_SWITCH :=1
-	CFG_BOOT_TIME_PROFILE :=0
+	CFG_UART_DYNAMIC_SWITCH :=0
+	CFG_BOOT_TIME_PROFILE :=1
 else
 	CFG_UART_DYNAMIC_SWITCH :=0
 	CFG_BOOT_TIME_PROFILE :=0
@@ -135,7 +135,7 @@ endif
 # LOG_LEVEL_DEBUG      (4)
 # Any log messages with levels less than and equal to this will be printed.
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-CFG_LOG_LEVEL :=0
+CFG_LOG_LEVEL :=4
 else
 CFG_LOG_LEVEL :=0
 endif
--- a/platform/common/partition/part_common.c
+++ b/platform/common/partition/part_common.c
@@ -56,6 +56,7 @@
 
 #define AB_TAG_SZ     (2)
 
+#define MOD     "[PART]"
 #ifdef MTK_PARTITION_COMMON
 static u8 g_cur_part_name[32] = {0};

固定频率800MHz

--- a/platform/ac8257/src/drivers/inc/dramc_pi_api.h
+++ b/platform/ac8257/src/drivers/inc/dramc_pi_api.h
@@ -108,19 +108,19 @@
     #define LP4_LOWEST_FREQSEL   (LP4_DDR1600)
 #else //LP4_HIGHEST_DDR3200
     #define LP4_HIGHEST_FREQ      (1600)
-    #define LP4_MIDDLE_FREQ        (1200)
+    #define LP4_MIDDLE_FREQ        (800)
     #define LP4_LOWEST_FREQ        (800)
     #define LP4_HIGHEST_FREQSEL   (LP4_DDR3200)
-    #define LP4_MIDDLE_FREQSEL     (LP4_DDR2400)
+    #define LP4_MIDDLE_FREQSEL     (LP4_DDR1600)
     #define LP4_LOWEST_FREQSEL   (LP4_DDR1600)
 #endif

 // 2400 workaround for fcMerlot only
 #ifdef MTK_LP4_HIGHEST_DDR2400
     #undef LP4_HIGHEST_FREQ
-    #define LP4_HIGHEST_FREQ 1200
+    #define LP4_HIGHEST_FREQ 800
     #undef LP4_HIGHEST_FREQSEL
-    #define LP4_HIGHEST_FREQSEL (LP4_DDR2400)
+    #define LP4_HIGHEST_FREQSEL (LP4_DDR1600)
 #endif

BWMZFX32H2A-8G-X

--- a/platform/ac8257/src/drivers/dramc_pi_basic_api.c
+++ b/platform/ac8257/src/drivers/dramc_pi_basic_api.c
@@ -7754,6 +7754,9 @@ void vDramcACTimingOptimize(DRAMC_CTX_T *p)
             case 0x1:   //6Gb per die  (3Gb per channel),  tRFCab=180
             case 0x2:   //8Gb per die  (4Gb per channel),  tRFCab=180
                 u1RFCabGrpIdx = tRFCAB_180;
+                if (p->support_rank_num == RANK_SINGLE && p->density == 2 && p->vendor_id == 0xff && p->revision_id == 0x87) {
+                    u1RFCabGrpIdx = tRFCAB_280; // for BW case
+                }
                 break;
             case 0x3:   //12Gb per die (6Gb per channel),  tRFCab=280
             case 0x4:   //16Gb per die (8Gb per channel),  tRFCab=280

BROM

--- a/platform/ac8257/src/drivers/platform.c
+++ b/platform/ac8257/src/drivers/platform.c
@@ -1479,6 +1479,10 @@ void platform_init(void)

 #endif

+   if (BR_RTC == g_boot_reason) {
+       platform_error_handler();
+   }
+
 #if !CFG_FPGA_PLATFORM

 #ifndef ATC_BOOTTIME_ENHANCEMENT

CFG_USB_UART_SWITCH

platform/ac8257/src/drivers/platform.c platform_pre_init

1340 #if !CFG_FPGA_PLATFORM
1341     #if (CFG_USB_UART_SWITCH)
1342     if (is_uart_cable_inserted()) {
1343         pal_log_info("\n%s Switch to UART Mode\n", MOD);
1344         set_to_uart_mode();
1345     } else {
1346         pal_log_info("\n%s Keep stay in USB Mode\n", MOD);
1347     }
1348     BOOTING_TIME_PROFILING_LOG("USB SWITCH to UART");
1349     #endif
1350 #endif

日志

串口号

--- a/custom/ac8257_demo_1g_32/cust_bldr.mak
+++ b/custom/ac8257_demo_1g_32/cust_bldr.mak
@@ -3,8 +3,8 @@
 ###################################################################
 CFG_BOOT_DEV :=BOOTDEV_SDMMC

-CFG_UART_LOG :=UART1
-CFG_UART_META :=UART1
+CFG_UART_LOG :=UART3
+CFG_UART_META :=UART3

 #ATF log only enable in eng mode
 ifeq ("$(TARGET_BUILD_VARIANT)","eng")

开关、等级

--- a/platform/ac8257/default.mak
+++ b/platform/ac8257/default.mak
@@ -111,7 +111,7 @@ CFG_PMIC_FULL_RESET :=0

 # dynamic switch UART log and profile boot time in user load
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-       CFG_UART_DYNAMIC_SWITCH :=1
+       CFG_UART_DYNAMIC_SWITCH :=0
        CFG_BOOT_TIME_PROFILE :=0
 else
        CFG_UART_DYNAMIC_SWITCH :=0
@@ -135,7 +135,7 @@ endif
 # LOG_LEVEL_DEBUG      (4)
 # Any log messages with levels less than and equal to this will be printed.
 ifeq ("$(TARGET_BUILD_VARIANT)","user")
-CFG_LOG_LEVEL :=0
+CFG_LOG_LEVEL :=3
 else
 CFG_LOG_LEVEL :=0
 endif

/proc/pl_lk

PL_LOG_STORE

--- a/custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk
+++ b/custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk
@@ -39,7 +39,7 @@ endif

 ATC_AOSP_ENHANCEMENT=yes
 ATC_USBHANDSHAKE_DIS=no
-ATC_BOOTTIME_ENHANCEMENT=yes
+ATC_BOOTTIME_ENHANCEMENT=no
 MTK_LP4_HIGHEST_DDR2400=yes

 ifeq ($(ENABLE_AB_UPDATE), yes)

memory test

触发方式

UART

输入字符串

USB ttyACM0

/dev/ttyACM0发送FASTBOOT，preloader判断g_boot_mode == FASTBOOT。

USB adb

adb reboot recovery，preloader判断g_boot_reason == BR_RTC。

GPIO

根据3秒内GPIO管脚跳变次数来决定模式。

#define GPIO_ACC    GPIO5
#define GPIO_DRV_VBUS   GPIO42
#define GPIO_VOL_A	GPIO110
#define GPIO_VOL_B	GPIO112
#define GPIO_LED    GPIO152
#define GPIO_LCD_BL GPIO173
#define CHECK_INTERVAL  100

int get_mode_by_gpio(u32 timeout)
{
    ulong start_time, current_time;
    int last_state, current_state;
    int change_count = 0;

    mt_set_gpio_mode(GPIO_ACC, GPIO_MODE_00);
    mt_set_gpio_dir(GPIO_ACC, GPIO_DIR_IN);

    mt_set_gpio_mode(GPIO_VOL_A, GPIO_MODE_00);
    mt_set_gpio_dir(GPIO_VOL_A, GPIO_DIR_IN);
    mt_set_gpio_mode(GPIO_VOL_B, GPIO_MODE_00);
    mt_set_gpio_dir(GPIO_VOL_B, GPIO_DIR_IN);

    mt_set_gpio_mode(GPIO_LED, GPIO_MODE_00);
    mt_set_gpio_dir(GPIO_LED, GPIO_DIR_OUT);

    mt_set_gpio_mode(GPIO_LCD_BL, GPIO_MODE_00);
    mt_set_gpio_dir(GPIO_LCD_BL, GPIO_DIR_OUT);

    last_state = mt_get_gpio_in(GPIO_ACC);
    mt_set_gpio_out(GPIO_LED, !last_state);
    mt_set_gpio_out(GPIO_LCD_BL, !last_state);

    print("detection for %d ms...\n", timeout);
    start_time = get_timer(0);

    while (1) {
        current_time = get_timer(0);
        if (current_time - start_time >= timeout) {
            break;
        }

        current_state = mt_get_gpio_in(GPIO_ACC);
        current_state |= mt_get_gpio_in(GPIO_VOL_A)<<1;
        current_state |= mt_get_gpio_in(GPIO_VOL_B)<<2;

        if (current_state != last_state) {
            mt_set_gpio_out(GPIO_LED, change_count&0x1);
            mt_set_gpio_out(GPIO_LCD_BL, change_count&0x1);
            change_count++;
            last_state = current_state;
            print("%dms: %d 0x%x\n", current_time - start_time,
                   change_count, current_state);
        }

        mdelay(CHECK_INTERVAL);
    }

    return change_count>>1;
}

memory.c

--- a/platform/ac8257/src/drivers/memory.c
+++ b/platform/ac8257/src/drivers/memory.c
@@ -36,6 +36,8 @@

 #include "typedefs.h"
 #include "platform.h"
+#include "gpio.h"
+#include "gpio_const.h"

 #include "memory.h"
 #include "emi.h"
@@ -190,6 +192,7 @@ void mt_mem_init(void)
        dram_fatal_exception_detection_end();
 #endif

+memory_test();
 #endif
 }

int memory_test(void)
{
    int i;
    u64 rank_size[2] = {0, 0};
    int rval;
    int mode;

    /* disable external watchdog */
    mt_set_gpio_mode(GPIO_DRV_VBUS, GPIO_MODE_00);
    mt_set_gpio_dir (GPIO_DRV_VBUS, GPIO_DIR_OUT);
    mt_set_gpio_out (GPIO_DRV_VBUS, GPIO_OUT_ZERO);

    mode = get_mode_by_gpio();
    print("mode: %d\n", mode);
    if (mode < 1) return 0;

    get_dram_rank_size(rank_size);
    print("%d: memory test start, rank size 0x%x 0x%x\n", get_timer(0), rank_size[0], rank_size[1]);
    mtk_wdt_disable();
    if (1 == mode) {
        rval = memory_pattern_test(0x40000000, rank_size[0]+rank_size[1]);
    } else {
        rval = complex_mem_test(0x40000000, rank_size[0]+rank_size[1]);
    }
    mtk_wdt_enable();
    mt_set_gpio_out (GPIO_LED, GPIO_OUT_ZERO);
    print("%d: memory test end\n", get_timer(0));
    print ("[%s] test %s\n", MOD, 0==rval?"pass":"fail");

    return 0;
}

debug UART log

complex test

11908: complex test, rank size 0x40000000 0x00000000
11908: loop 0 sectional
11908: offset 0x00000000 ... pass, 0
73457: offset 0x02000000 ... pass, 0
135005: offset 0x04000000 ... pass, 0
196553: offset 0x06000000 ... pass, 0
258101: offset 0x08000000 ... pass, 0
319649: offset 0x0A000000 ... pass, 0
381197: offset 0x0C000000 ... fail, -22
438827: offset 0x0E000000 ... fail, -23
499618: offset 0x10000000 ... pass, 0
561166: offset 0x12000000 ... pass, 0
622713: offset 0x14000000 ... pass, 0
684260: offset 0x16000000 ... pass, 0
745808: offset 0x18000000 ... fail, -6
767027: offset 0x1A000000 ... pass, 0
828574: offset 0x1C000000 ... pass, 0
890122: offset 0x1E000000 ... pass, 0
951669: offset 0x20000000 ... fail, -4
963435: offset 0x22000000 ... fail, -23
1023699: offset 0x24000000 ... fail, -1
1024651: offset 0x26000000 ... fail, -4
1035677: offset 0x28000000 ... pass, 0
1097224: offset 0x2A000000 ... fail, -18
1139873: offset 0x2C000000 ... fail, -22
1195989: offset 0x2E000000 ... pass, 0
1257536: offset 0x30000000 ... pass, 0
1319082: offset 0x32000000 ... pass, 0
1380629: offset 0x34000000 ... fail, -4
1395075: offset 0x36000000 ... pass, 0
1456622: offset 0x38000000 ... fail, -4
1473516: offset 0x3A000000 ... pass, 0
1535063: offset 0x3C000000 ... fail, -4
1548061: offset 0x3E000000 ... fail, -4

pattern test

flip test

12896: bitflip test, rank size 0x40000000 0x00000000
12897: loop 0
12897: offset 0x00000000 ...
259019: offset 0x02000000 ...
505141: offset 0x04000000 ...
751263: offset 0x06000000 ...
997384: offset 0x08000000 ...
1243506: offset 0x0A000000 ...
1489627: offset 0x0C000000 ...
1735749: offset 0x0E000000 ...
1981871: offset 0x10000000 ...
2227992: offset 0x12000000 ...
2474113: offset 0x14000000 ...
2720234: offset 0x16000000 ...
2966356: offset 0x18000000 ...
3212477: offset 0x1A000000 ...
3458599: offset 0x1C000000 ...
3704721: offset 0x1E000000 ...
3950841: offset 0x20000000 ...
4196962: offset 0x22000000 ...
4443082: offset 0x24000000 ...
4689203: offset 0x26000000 ...
4935323: offset 0x28000000 ...
5181443: offset 0x2A000000 ...
5427564: offset 0x2C000000 ...
5673686: offset 0x2E000000 ...
5919807: offset 0x30000000 ...
6165929: offset 0x32000000 ...
6412050: offset 0x34000000 ...
6658170: offset 0x36000000 ...
6904291: offset 0x38000000 ...
7150412: offset 0x3A000000 ...
7396534: offset 0x3C000000 ...
0x00000001 != 0x00000000
check again: 0x00000001, 0x00000000
bitflip error at bit 0, pattern 0x00000001, offset 0x7CC00000
7402389: offset 0x3E000000 ...
0x00000001 != 0x00000000
check again: 0x00000001, 0x00000000
bitflip error at bit 0, pattern 0x00000001, offset 0x7E400000

normal

sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass
[PWRAP] InitSiStrobe (5, 5, DA65) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 5)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x152A (Last one command addr)
[PWRAP] RECORD_WDATA0:0x2D (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x170E (Last second command addr)
[PWRAP] RECORD_WDATA1:0x78 (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x152A (Last third command addr)
[PWRAP] RECORD_WDATA2:0x1D (Last third command wdata)
[PWRAP] init pass, ret=0.

DATE_CODE_YY:0, DATE_CODE_WW:0
[SegCode] Segment Code:0x0, PROJECT_CODE:0x0, FAB_CODE:0x0, RW_STA:0x0, CTL:0x0, DCM:0x4
[PMIC]Preloader Start
[PMIC]AC8257 CHIP Code = 0x5721, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x4B
[PMIC]PONSTS[0xC]=0xE
[PMIC]POFFSTS[0xE]=0x1
[PMIC]PGSTATUS0[0x14]=0xFFFE
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x11F
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xA1C]=0x0
[PMIC]TOP_RST_MISC[0x14C]=0x1304
[PMIC]TOP_CLK_TRIM[0x38E]=0x6CC0
latch VPROC 650000 uV
latch VSRAM_PROC 900000 uV
latch VSRAM_OTHERS 800000 uV
latch VCORE 800000 uV
latch VMODEM 800000 uV
[pmic_check_rst] UVLO_RSTB
[PMIC]just_rst = 0
No EFUSE SW Load
battery exists
[PMIC]disable usbdl wo battery
[PMIC]pmic_wdt_set Reg[0x14C]=0x1325
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
[PMIC]Init done
[PMIC] pmic_init_setting end. v180413
[AC8257] 1 6,61
[AC8257] 1 2,45
[AC8257] 1 1,48
[AC8257] get volt 5, 61, 900000
vsram_others = 900000 uV
[AC8257] get volt 3, 45, 800000
vproc = 800000 uV
[AC8257] get volt 6, 61, 900000
vsram_proc = 900000 uV
[AC8257] get volt 2, 45, 800000
vcore = 800000 uV
[AC8257] get volt 1, 48, 800000
vmodem = 800000 uV
[AC8257] 2 6,1
[AC8257] 2 5,1
[AC8257] 2 3,1
[AC8257] 2 2,1
[AC8257] 2 1,1
[DDR Reserve] ddr reserve mode not be enabled yet
[PMIC]POWER_HOLD :0x1
Enter mtk_kpd_gpio_set!
mtk detect key function pmic_detect_homekey MTK_PMIC_RST_KEY = 17

welcome to lk/MP

boot args 0x12c0000 0x47da3ee0 0x7c 0x0
INIT: cpu 0, calling hook 0x55b54075 (vm_preheap) at level 0x3ffff, flags 0x1
initializing heap
calling constructors
initializing kernel
INIT: cpu 0, calling hook 0x55b541b1 (vm) at level 0x50000, flags 0x1
INIT: cpu 0, calling hook 0x55b403d5 (bootargs_init) at level 0x50001, flags 0x1
tee_args->magic: 0x4b54444d
tee_args->version: 0x1
tee_args->NWEntry: 0x0
tee_args->NWBootArgs: 0x0
tee_args->NWBootArgsSize: 0x0
tee_args->dRamBase: 0x40000000
tee_args->dRamSize: 0x40000000
tee_args->secDRamBase: 0x55b40000
tee_args->secDRamSize: 0x12c0000
tee_args->sRamBase: 0x0
tee_args->sRamSize: 0x0
tee_args->secSRamBase: 0x0
tee_args->secSRamSize: 0x0
tee_args->gicd_base: 0xc000000
tee_args->gicr_base: 0xc080000
tee_args->gic_ver: 0x0
tee_args->log_port: 0x11002000
tee_args->log_baudrate: 0xe1000
INIT: cpu 0, calling hook 0x55b405c3 (platform_after_vm) at level 0x50002, flags 0x1
gicd 0xc000000, gicr 0xc080000
gicdv 0xff200000, gicrv 0xff000000
INIT: cpu 0, calling hook 0x55b455d5 (platform_after_vm_hacc_init) at level 0x50003, flags 0x1
Enable mmap for HACC!
INIT: cpu 0, calling hook 0x55b456f9 (platform_after_vm_trng_init) at level 0x50003, flags 0x1
Enable mmap for HWTRNG!
INIT: cpu 0, calling hook 0x55b52d8b (platform_after_vm_hkdf_unittest) at level 0x50004, flags 0x1
HKDF-SHA256 Verification: PASS
initializing mp
initializing threads
initializing timers
initializing ports
creating bootstrap completion thread
top of bootstrap2()
creating bootstrap completion thread for cpu 1
creating bootstrap completion thread for cpu 2
creating bootstrap completion thread for cpu 3
releasing 3 secondary cpus
initializing platform
INIT: cpu 0, calling hook 0x55b4988b (libsm_cpu) at level 0x8fffe, flags 0x3
INIT: cpu 0, calling hook 0x55b49985 (libsm) at level 0x8ffff, flags 0x1
initializing target
calling apps_init()
INIT: cpu 0, calling hook 0x55b567b5 (LibTomCryptInit) at level 0xa0020, flags 0x1
INIT: cpu 0, calling hook 0x55b4c98b (uctx) at level 0xafffe, flags 0x1
als_slot_cnt 1 ret 1
INIT: cpu 0, calling hook 0x55b51cf1 (tipc_init) at level 0xafffe, flags 0x1
INIT: cpu 0, calling hook 0x55b4a2df (libtrusty) at level 0xaffff, flags 0x1
initializing trusty (Built: 03:35:41 Mar 13 2025)
trusty_app: start 0x55b82000 size 0x0000f000 end 0x55b91000
trusty_app 0 uuid: 0x38ba0cdc 0xdf0e 0x11e4 0x9869 0x233fb6ae4795
trusty_app: start 0x55b91000 size 0x00086000 end 0x55c17000
trusty_app 1 uuid: 0x5f902ace 0x5e5c 0x4cd8 0xae54 0x87b88c22ddaf
trusty_app: start 0x55c17000 size 0x00027000 end 0x55c3e000
trusty_app 2 uuid: 0xcea8706d 0x6cb4 0x49f3 0xb994 0x29e0e478bd29
trusty_app: start 0x55c3e000 size 0x00019000 end 0x55c57000
trusty_app 3 uuid: 0x7445ca05 0x35d5 0x4698 0xbb9a 0xd84f9a5fcf
INIT: cpu 0, calling hook 0x55b431df (atceinfo) at level 0xb0000, flags 0x1
Info:atceinfo:init...
Debug:atccrypt:import_rsakey success!
Info:atceinfo:init finished
INIT: cpu 0, calling hook 0x55b43f27 (atcencrypt_service) at level 0xb0000, flags 0x1
init_atcencrypt_service enter
Info: atcencrypt_ipc_thread waiting
init_atcencrypt_service finish
INIT: cpu 0, calling hook 0x55b49635 (memlog) at level 0xb0000, flags 0x1
INIT: cpu 0, calling hook 0x55b501d7 (trusty_smcall) at level 0xb0000, flags 0x1
Initializing Trusted OS SMC handler
INIT: cpu 0, calling hook 0x55b51e29 (kmgetboot_service) at level 0xb0000, flags 0x1
status_t init_kmgetboot_ipc(void):569: com.mediatek.kmgetboot created
INIT: cpu 0, calling hook 0x55b5219d (mtcrypto_service) at level 0xb0000, flags 0x1
INIT: cpu 0, calling hook 0x55b53263 (trusty_mt_smcall) at level 0xb0000, flags 0x1
Initializing MTK SMC handler
INIT: cpu 0, calling hook 0x55b4aae1 (libtrusty_apps) at level 0xb0001, flags 0x1
INIT: cpu 0, calling hook 0x55b406ad (disable_uart_after_bootup) at level 0xffffffff, flags 0x1
Disable UART after Trusty bootup!

fatal dram exception

sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass
[PWRAP] InitSiStrobe (5, 5, 9A65) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 5)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x0 (Last one command addr)
[PWRAP] RECORD_WDATA0:0x0 (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x0 (Last second command addr)
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x0 (Last third command addr)
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata)
[PWRAP] init pass, ret=0.

DATE_CODE_YY:0, DATE_CODE_WW:0
[SegCode] Segment Code:0x0, PROJECT_CODE:0x0, FAB_CODE:0x0, RW_STA:0x0, CTL:0x0, DCM:0x4
[PMIC]Preloader Start
[PMIC]AC8257 CHIP Code = 0x5721, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x0
[PMIC]PONSTS[0xC]=0x4
[PMIC]POFFSTS[0xE]=0x0
[PMIC]PGSTATUS0[0x14]=0xFFFE
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x21F
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xA1C]=0x0
[PMIC]TOP_RST_MISC[0x14C]=0x200
[PMIC]TOP_CLK_TRIM[0x38E]=0x6CC0
latch VPROC 800000 uV
latch VSRAM_PROC 1068750 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 800000 uV
[pmic_check_rst] PORSTB
[PMIC]just_rst = 0
No EFUSE SW Load
battery exists
[PMIC]disable usbdl wo battery
[PMIC]pmic_wdt_set Reg[0x14C]=0x221
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
[PMIC]Init done
[PMIC] pmic_init_setting end. v180413
[AC8257] 1 6,61
[AC8257] 1 2,45
[AC8257] 1 1,48
[AC8257] get volt 5, 61, 900000
vsram_others = 900000 uV
[AC8257] get volt 3, 45, 800000
vproc = 800000 uV
[AC8257] get volt 6, 61, 900000
vsram_proc = 900000 uV
[AC8257] get volt 2, 45, 800000
vcore = 800000 uV
[AC8257] get volt 1, 48, 800000
vmodem = 800000 uV
[AC8257] 2 6,1
[AC8257] 2 5,1
[AC8257] 2 3,1
[AC8257] 2 2,1
[AC8257] 2 1,1
[DDR Reserve] ddr reserve mode not be enabled yet
[PMIC]POWER_HOLD :0x1
Enter mtk_kpd_gpio_set! 
mtk detect key function pmic_detect_homekey MTK_PMIC_RST_KEY = 17

mtk detect key function pmic_detect_homekey pressed
[dramc] init partition address is 0x0000000000008000
[dramc] init SRAM region for DRAM exception detection
[dramc] LAST_DRAM_FATAL_ERR_FLAG = 0x0
for cold boot, always return 0
[AC8257] 4 2,1
[AC8257] 2 7,0
enable RT5738_VDD2 fail (ret = 0)
[EMI] mcp_dram_num:0,discrete_dram_num:6,enable_combo_dis:1
[MDL]index:0, MR5:1, type:5, vender_id:13
[MDL]index:1, MR5:1, type:5, vender_id:13
[MDL]index:2, MR5:FF, type:5, vender_id:13
[MDL]index:3, MR5:13, type:5, vender_id:13
found:1,i:3
[EMI] MDL number = 3
[AC8257] 1 2,25
Read voltage for 800
Vio18 = 1810000
[AC8257] get volt 2, 25, 675000
Vcore = 675000
Vdram = 0
[AC8257] 1 2,37
Read voltage for 1200
Vio18 = 1810000
[AC8257] get volt 2, 37, 750000
Vcore = 750000
Vdram = 0
[AC8257] 1 2,37
Read voltage for 1200
Vio18 = 1810000
[AC8257] get volt 2, 37, 750000
Vcore = 750000
Vdram = 0
[AC8257] 4 2,0
[AC8257] 1 2,45
[AC8257] get volt 2, 45, 800000
Vcore = 800000
[MEM] 1st complex R/W mem test fail :FFFFFFFF (start addr:0x48000000)
[LastDRAMC] 0x10E40C: 0x19870611
[LastDRAMC] 0x10E410: 0x0
[LastDRAMC] 0x10E414: 0x0
[LastDRAMC] 0x10E418: 0x19870611
[LastDRAMC] 0x10E41C: 0x0
[LastDRAMC] 0x10E420: 0x0
[LastDRAMC] 0x10E424: 0x80000000
[LastDRAMC] 0x10E428: 0x0
[LastDRAMC] 0x10E42C: 0x402AD3B2
[LastDRAMC] 0x10E430: 0x886F36EC
[LastDRAMC] 0x10E434: 0x118578A
[LastDRAMC] 0x10E438: 0x35DE10FC
[LastDRAMC] 0x10E43C: 0x0
[LastDRAMC] 0x10E440: 0x0
[LastDRAMC] 0x10E444: 0x0
[LastDRAMC] 0x10E448: 0x0
[LastDRAMC] 0x10E44C: 0xFB5CFEEA
[LastDRAMC] 0x10E450: 0xB71B0
[LastDRAMC] 0x10E454: 0xA4CB8
[dramc] DRAM_FATAL_ERR_FLAG = 0x80000020
[dramc] fatal dram exception found! reset system..

android 11

Pll init start...
Pll init Done!
[PWRAP] si_en_sel = 0, si_ck_sel = 0, si_sample_ctrl = 0, rdata = 96A9
[PWRAP] si_en_sel = 0, si_ck_sel = 1, si_sample_ctrl = 20, rdata = 5AA5, Pass
[PWRAP] InitSiStrobe (5, 5, DA65) Data Boundary Is Found !!
[PWRAP] SI Strobe Calibration For PMIC 0 Done, (40, 5)
[PWRAP] Read Test pass, return_value=0x0
[PWRAP] Write Test pass
[PWRAP] RECORD_CMD0:  0x0 (Last one command addr)
[PWRAP] RECORD_WDATA0:0x0 (Last one command wdata)
[PWRAP] RECORD_CMD1:  0x0 (Last second command addr)
[PWRAP] RECORD_WDATA1:0x0 (Last second command wdata)
[PWRAP] RECORD_CMD2:  0x0 (Last third command addr)
[PWRAP] RECORD_WDATA2:0x0 (Last third command wdata)
[PWRAP] init pass, ret=0.

DATE_CODE_YY:0, DATE_CODE_WW:0
[SegCode] Segment Code:0x0, PROJECT_CODE:0x0, FAB_CODE:0x0, RW_STA:0x0, CTL:0x0, DCM:0x4
[PMIC]Preloader Start
[PMIC]AC8X CHIP Code = 0x5721, mrv=1
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x152]=0x0
[PMIC]PONSTS[0xC]=0x4
[PMIC]POFFSTS[0xE]=0x0
[PMIC]PGSTATUS0[0x14]=0xFFFE
[PMIC]PSOCSTATUS[0x16]=0x0
[PMIC]BUCK_OC_SDN_STATUS[0x1434]=0x0
[PMIC]BUCK_OC_SDN_EN[0x1444]=0x29F
[PMIC]THERMALSTATUS[0x18]=0x0
[PMIC]STRUP_CON4[0xA1C]=0x0
[PMIC]TOP_RST_MISC[0x14C]=0x200
[PMIC]TOP_CLK_TRIM[0x38E]=0x6CC0
latch VPROC 800000 uV
latch VSRAM_PROC 1068750 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 800000 uV
[pmic_check_rst] PORSTB
[PMIC]just_rst = 0
No EFUSE SW Load
ignore bat check
[PMIC]disable usbdl wo battery
[PMIC]pmic_wdt_set Reg[0x14C]=0x221
register vs1 OK
register vmodem OK
register vcore OK
register vproc OK
register vpa OK
register vsram_others OK
register vsram_proc OK
register vdram OK
[PMIC]Init done
clk_buf_dump_dts_log: PMIC_CLK_BUF?_STATUS=2 1 1 2 0 0 0
clk_buf_dump_dts_log: PMIC_CLK_BUF?_DRV_CURR=1 1 1 1 1 1 1
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x6B6D 386A AD00 9829 A2B5 A19A A8AA 11 1
clk_buf_dump_clkbuf_log DCXO_CW00/02/11/13/14/15/16/20/top_spi_con1=0x4F1D 386A 8000 98E9 A2B5 A2AA 9455 11 0
clk_buf_init_pmic_wrap: DCXO_CONN_ADR0/WDATA0/ADR1/WDATA1=0x44A/0/44A/1
clk_buf_init_pmic_wrap: DCXO_NFC_ADR0/WDATA0/ADR1/WDATA1/EN=0x78C/100/78A/100/3
[PMIC] pmic_init_setting end. v180413
[AC8X] 1 6,61
[AC8X] 1 2,45
[AC8X] 1 1,48
[AC8X] get volt 5, 61, 900000
vsram_others = 900000 uV
[AC8X] get volt 3, 45, 800000
vproc = 800000 uV
[AC8X] get volt 6, 61, 900000
vsram_proc = 900000 uV
[AC8X] get volt 2, 45, 800000
vcore = 800000 uV
[AC8X] get volt 1, 48, 800000
vmodem = 800000 uV
[AC8X] 2 6,1
[AC8X] 2 5,1
[AC8X] 2 3,1
[AC8X] 2 2,1
[AC8X] 2 1,1
[DDR Reserve] ddr reserve mode not be enabled yet
Enter mtk_kpd_gpio_set!
after set KP enable: KP_SEL = 0x1C70 !
[PMIC]POWER_HOLD :0x1
pl chr:1 monitor:1 plchr:1 gain:1042
mtk_kpd_gpio_set Already!
mtk detect key function pmic_detect_homekey MTK_PMIC_RST_KEY = 17
I/TC:
I/TC: OP-TEE version: 7f97f9e (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #1 Wed Jun 25 04:02:38 UTC 2025 aarch64
I/TC: Primary CPU initializing
I/TC: Primary CPU switching to normal world boot
I/TC: Secondary CPU 1 initializing
I/TC: Secondary CPU 1 switching to normal world boot
I/TC: Secondary CPU 2 initializing
I/TC: Secondary CPU 2 switching to normal world boot
I/TC: Secondary CPU 3 initializing
I/TC: Secondary CPU 3 switching to normal world boot
E/TC:2 0 std_smc_entry:169 Unknown SMC 0x32000014
E/TC:2 0 std_smc_entry:169 Unknown SMC 0x32000016
I/TC: RPMB: Using AutoChips customized key
E/TC:? 0 tee_rpmb_verify_key_sync_counter:1031 Verify key returning 0xffff000f
I/TC: Verify uuid derived key failed!, try to use common key
D/TA:  TA_CreateEntryPoint:48 TA_CreateEntryPoint 48
D/TA:  TA_create_secret_key:100 TA_create_secret_key 100
D/TA:  TA_InitializeAuthTokenKey:37 Checking auth_token key secret
D/TA:  TA_InitializeAuthTokenKey:72 auth_token key secret is already created
D/TA:  TA_OpenSessionEntryPoint:90 TA_OpenSessionEntryPoint 90
D/TA:  TA_InvokeCommandEntryPoint:1464 KM_CONFIGURE
D/TA:  TA_configure:153 TA_configure 153
D/TA:  TA_serialize_rsp_err:432 res: 0
D/TA:  TA_CreateEntryPoint:89 eTA: CreateEntryPoint
D/TA:  TA_OpenSessionEntryPoint:118 eTA: OpenSessionEntryPoint
I/TA: eTA: OpenSession Success!
D/TA:  TA_InvokeCommandEntryPoint:156 eTA: InvokeCommand 4
D/TA:  plat_check_approve:124 eTA: plat_check_approve entry
I/TA: eTA: plat check module-AVM-00 result-0x0
D/TA:  atceinfo_handle_approve:288 eTA: Put AVM-00 in 1
D/TA:  TA_InvokeCommandEntryPoint:156 eTA: InvokeCommand 6
I/TA: eTA: Say Goodbye!
D/TA:  TA_DestroyEntryPoint:100 eTA: DestroyEntryPoint
D/TA:  TA_CreateEntryPoint:33 Checking master key secret
D/TA:  TA_CreateEntryPoint:55 Secret is already created

download

CMD

platform/ac8257/src/core/inc/download.h

 48 #define CMD_ZEROIZATION            0xf0
 49 #define CMD_GET_PL_CAP             0xfb
 50 #define CMD_GET_HW_SW_VER          0xfc
 51 #define CMD_GET_HW_CODE            0xfd
 52 #define CMD_GET_BL_VER             0xfe
 53
 54 #define CMD_LEGACY_WRITE           0xa1
 55 #define CMD_LEGACY_READ            0xa2
 56
 57 #define CMD_I2C_INIT               0xB0
 58 #define CMD_I2C_DEINIT             0xB1
 59 #define CMD_I2C_WRITE8             0xB2
 60 #define CMD_I2C_READ8              0xB3
 61 #define CMD_I2C_SET_SPEED          0xB4
 62
 63 #define CMD_PWR_INIT               0xC4
 64 #define CMD_PWR_DEINIT             0xC5
 65 #define CMD_PWR_READ16             0xC6
 66 #define CMD_PWR_WRITE16            0xC7
 67
 68 #define CMD_READ16                 0xD0
 69 #define CMD_READ32                 0xD1
 70 #define CMD_WRITE16                0xD2
 71 #define CMD_WRITE16_NO_ECHO        0xD3
 72 #define CMD_WRITE32                0xD4
 73 #define CMD_JUMP_DA                0xD5
 74 #define CMD_JUMP_BL                0xD6
 75 #define CMD_SEND_DA                0xD7
 76 #define CMD_GET_TARGET_CONFIG      0xD8
 77 #define CMD_UART1_LOG_EN           0xDB
 78
 79 #define CMD_GET_ME_ID              0xE1
 80 #define CMD_GET_SOC_ID             0xE7
 81
 82 #if CFG_PRELOADER_AS_DA
 83 #define CMD_SEND_IMAGE             0x70
 84 #define CMD_BOOT_IMAGE             0x71
 85 #endif
 86
 87 #define CMD_STAY_STILL            0x80

ac82757发READY，主机发a00a5005 ，ac82757发5ff5affa。获取到BL_VER preloader mode，命令回显brom mode，brom mode会获取ME ID、SOC ID。

	CMD
fe	CMD_GET_BL_VER	ver
e1	CMD_GET_ME_ID	len	ME ID	status
fd	CMD_GET_HW_CODE	hwcode	status
fc	CMD_GET_HW_SW_VER	APHW_SUBCODE	APHW_VER	APSW_VER	status
d1	CMD_READ32	addr	len	status	data	status
df	BROM log message	len	log	status
e7	CMD_GET_SOC_ID	len	SOC ID	status
d8	CMD_GET_TARGET_CONFIG	security config	status
d7	CMD_SEND_DA	da_addr	da_len	sig_len	data	chksum16	status
d5	CMD_JUMP_DA	da_addr	status

DA CMD

CMD	control code	CC_	debug UART
0x10100		SPECIAL_CMD_SETUP_ENVIRONMENT
0x10101		SPECIAL_CMD_SETUP_HW_INIT_PARAMS
0x10009		CMD_DEVICE_CTRL
0x10009	0x40011	GET_EXPIRE_DATE
	0x20004	SET_RESET_KEY
	0x20002	SET_BATTERY_OPT	devc_set_battery_opt
	0x20003	SET_CHECKSUM_LEVEL	devc_set_checksum_level
	0x4000a	GET_CONNECTION_AGENT	devc_get_connection_agent
	0x4000c	GET_RAM_INFO	devc_get_ram_info
	0x40001	GET_EMMC_INFO	devc_get_emmc_info
	0x40002	GET_NAND_INFO
	0x40003	GET_NOR_INFO
	0x40004	GET_UFS_INFO	devc_get_ufs_info
	0x4000d	GET_CHIP_ID	devc_get_chip_baseband
	0xe0003	CTRL_READ_REGISTER
	0xe0008	GET_RAMDOM_ID
	0x4000b	GET_USB_SPEED	devc_get_usb_speed
	0xe0002	CTRL_RAM_TEST	devc_ctrl_ram_test
0x10007		CMD_SHUTDOWN

usbdl

1041 void platform_safe_mode(int en, u32 timeout)
1042 {
1043 #if !CFG_FPGA_PLATFORM
1044
1045     U32 usbdlreg = 0;
1046
1047     /* if anything is wrong and caused wdt reset, enter bootrom download mode */
1048     timeout = !timeout ? USBDL_TIMEOUT_MAX : timeout / 1000;
1049     timeout <<= 2;
1050     timeout &= USBDL_TIMEOUT_MASK; /* usbdl timeout cannot exceed max value */
1051
1052     usbdlreg |= timeout;
1053     if (en)
1054         usbdlreg |= USBDL_BIT_EN;
1055     else
1056         usbdlreg &= ~USBDL_BIT_EN;
1057
1058     usbdlreg &= ~USBDL_BROM ;
1059     /*Add magic number for AC8257*/
1060     usbdlreg |= USBDL_MAGIC;
1061
1062     // set BOOT_MISC0 as watchdog resettable
1063     DRV_WriteReg32(MISC_LOCK_KEY,MISC_LOCK_KEY_MAGIC);
1064     DRV_SetReg32(RST_CON,1);
1065     DRV_WriteReg32(MISC_LOCK_KEY,0);
1066
1067     DRV_WriteReg32(USBDL_FLAG,usbdlreg);
1068
1069     return;
1070 #endif
1071
1072 }
1073
1074 #if CFG_EMERGENCY_DL_SUPPORT
1075 void platform_emergency_download(u32 timeout)
1076 {
1077     /* enter download mode */
1078     pal_log_info("%s emergency download mode(timeout: %ds).\n", MOD, timeout / 1000);
1079     platform_safe_mode(1, timeout);
1080
1081 #if !CFG_FPGA_PLATFORM
1082     mtk_arch_reset(0); /* don't bypass power key */
1083 #endif
1084
1085     while(1);
1086 }
1087 #endif

PAL_ASSERT

platform/pal/inc/pal_assert.h
    PAL_ASSERT
        platform_assert
platform/ac8257/src/drivers/platform.c
    platform_assert
        pal_log_err
        platform_error_handler
            platform_emergency_download

DRAM CALIBRATION

调试串口日志

[dramc] PL_VERSION is updated, erase the DRAM shu_data

header

platform/ac8257/src/drivers/inc/emi.h

493 #define DRAM_CALIBRATION_DATA_MAGIC 0x9502
494
495 typedef struct _DRAM_CALIBRATION_HEADER_T
496 {
497     u32 pl_version;
498     u16 magic_number;
499     u32 calib_err_code;
500 } DRAM_CALIBRATION_HEADER_T;
501
502 typedef struct _DRAM_CALIBRATION_MRR_DATA_T
503 {
504     u16 checksum;
505     u16 emi_checksum;
506     DRAM_INFO_BY_MRR_T DramInfo;
507 } DRAM_CALIBRATION_MRR_DATA_T;
508
509 typedef struct _DRAM_CALIBRATION_SHU_DATA_T
510 {
511     u16 checksum;
512     SAVE_TIME_FOR_CALIBRATION_T calibration_data;
513 } DRAM_CALIBRATION_SHU_DATA_T;
514
515 typedef struct _DRAM_CALIBRATION_DATA_T
516 {
517     DRAM_CALIBRATION_HEADER_T header;
518     DRAM_CALIBRATION_MRR_DATA_T mrr_info;
519     DRAM_CALIBRATION_SHU_DATA_T data[DRAM_DFS_SHUFFLE_MAX];
520 } DRAM_CALIBRATION_DATA_T;
521
522
523 /*
524  * g_dram_storage_api_err_code:
525  *  bit[0:3] -> read api
526  *  bit[4:7] -> write api
527  *  bit[8:11] -> clean api
528  *  bit[12:12] -> data formatted due to fatal exception
529  */
530 #define ERR_NULL_POINTER    (0x1)
531 #define ERR_MAGIC_NUMBER    (0x2)
532 #define ERR_CHECKSUM        (0x3)
533 #define ERR_PL_UPDATED      (0x4)
534 #define ERR_BLKDEV_NOT_FOUND    (0x5)
535 #define ERR_BLKDEV_READ_FAIL    (0x6)
536 #define ERR_BLKDEV_WRITE_FAIL   (0x7)
537 #define ERR_BLKDEV_NO_PART  (0x8)

PL_VERSION

platform/ac8257/src/core/inc/pl_version.h

38 #define PL_VERSION    0x02053215

platform/ac8257/src/drivers/inc/dramc_pi_api.h

dram info by mrr

  56 #define CHANNEL_NUM      2   // 1 single channel, 2 dual channel, 4 4 channel

 766 typedef enum
 767 {
 768     RANK_0= 0,
 769     RANK_1,
 770     RANK_MAX
 771 } DRAM_RANK_T;

1251 typedef struct _DRAM_INFO_BY_MRR_T
1252 {
1253     U16 u2MR5VendorID;
1254     U16 u2MR6RevisionID;
1255     U64 u8MR8Density[CHANNEL_NUM][RANK_MAX];
1256 } DRAM_INFO_BY_MRR_T;

save time for calibration

1110 typedef struct _SAVE_TIME_FOR_CALIBRATION_T
1111 {
1112     //U8 femmc_Ready;
1113
1114     // Calibration or not
1115     //U8 Bypass_TXWINDOW;
1116     //U8 Bypass_RXWINDOW;
1117     //U8 Bypass_RDDQC;
1118
1119     // delay cell time
1120     //U8 ucg_num_dlycell_perT_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM];
1121     //U16 u2gdelay_cell_ps_all[DRAM_DFS_SHUFFLE_MAX][CHANNEL_NUM];
1122     U8 ucnum_dlycell_perT;
1123     U16 u2DelayCellTimex100;
1124
1125     // CLK & DQS duty
1126     S8 s1ClockDuty_clk_delay_cell[CHANNEL_NUM][RANK_MAX];
1127     U8 u1clk_use_rev_bit;
1128     S8 s1DQSDuty_clk_delay_cell[CHANNEL_NUM][DQS_NUMBER_LP4];
1129     U8 u1dqs_use_rev_bit;
1130
1131     // CBT
1132     U8 u1CBTVref_Save[CHANNEL_NUM][RANK_MAX];
1133     U8 u1CBTClkDelay_Save[CHANNEL_NUM][RANK_MAX];
1134     U8 u1CBTCmdDelay_Save[CHANNEL_NUM][RANK_MAX];
1135     U8 u1CBTCsDelay_Save[CHANNEL_NUM][RANK_MAX];
1136     #if CA_PER_BIT_DELAY_CELL
1137     U8 u1CBTCA_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQS_BIT_NUMBER];
1138     #endif
1139
1140     // Write leveling
1141     U8 u1WriteLeveling_bypass_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];  //for bypass writeleveling
1142
1143     // Gating
1144     U8 u1Gating2T_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1145     U8 u1Gating05T_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1146     U8 u1Gatingfine_tune_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1147     U8 u1Gatingucpass_count_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1148
1149     // TX perbit
1150     U8 u1TxWindowPerbitVref_Save[CHANNEL_NUM][RANK_MAX];
1151     U16 u1TxCenter_min_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1152     U16 u1TxCenter_max_Save[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1153     U16 u1Txwin_center_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
1154     //U16 u1Txfirst_pass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
1155     //U16 u1Txlast_pass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
1156     //U8 u1TX_PerBit_DelayLine_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
1157
1158     // Datlat
1159     U8 u1RxDatlat_Save[CHANNEL_NUM][RANK_MAX];
1160
1161     // RX perbit
1162     U8 u1RxWinPerbitVref_Save[CHANNEL_NUM];
1163     U8 u1RxWinPerbit_DQS[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1164     U8 u1RxWinPerbit_DQM[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1165     U8 u1RxWinPerbit_DQ[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];
1166     //S16 u1RxWinPerbitDQ_firsbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];  //for bypass rxwindow
1167     //U8 u1RxWinPerbitDQ_lastbypass_Save[CHANNEL_NUM][RANK_MAX][DQ_DATA_WIDTH_LP4];  //for bypass rxwindow
1168
1169     //TX OE
1170     U8 u1TX_OE_DQ_MCK[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1171     U8 u1TX_OE_DQ_UI[CHANNEL_NUM][RANK_MAX][DQS_NUMBER_LP4];
1172
1173
1174 #if RUNTIME_SHMOO_RELEATED_FUNCTION
1175     U8 u1SwImpedanceResule[2][4];
1176     U32 u4TXRG_Backup[CHANNEL_NUM][RUNTIME_SHMOO_RG_BACKUP_NUM];
1177
1178     RUNTIME_SHMOO_SAVE_PARAMETER_T Runtime_Shmoo_para;
1179 #endif
1180 } SAVE_TIME_FOR_CALIBRATION_T;

platform/ac8257/src/drivers/emi.c

read_offline_dram_mdl_data
write_offline_dram_mdl_data
read_offline_dram_calibration_data

Init_DRAM
    DramcSave_Time_For_Cal_End
        write_offline_dram_calibration_data

mt_mem_init
    clean_dram_calibration_data

read_offline_dram_mdl_data

2269     if (hdr.pl_version != PL_VERSION) {
2270         /* current preloader version does not match the calibration hdr in storage -> erase the partition */
2271         dramc_crit("[dramc] PL_VERSION is updated, erase the DRAM shu_data\n");
2272
2273         shu_data.checksum = 0;
2274
2275         /* clear each shuffle */
2276         for (i = 0; i < DRAM_DFS_SHUFFLE_MAX; i++) {
2277             ret = blkdev_write(bootdev, part_dram_data_addr + ((unsigned long) &datap->data[i]), sizeof(shu_data), (u8*)&shu_data, PART_ID_DRAM_DATA     );
2278             if (ret != 0) {
2279                 dramc_crit("[dramc] blkdev_write failed\n");
2280                 dram_offline_data_flags = ERR_BLKDEV_WRITE_FAIL;
2281                 goto exit;
2282             }
2283         }
2284
2285         dram_offline_data_flags = ERR_PL_UPDATED;
2286         goto exit;
2287     }
2288
2289     /* check magic number */
2290     if (hdr.magic_number != DRAM_CALIBRATION_DATA_MAGIC) {
2291         dramc_crit("[dramc] magic number mismatch\n");
2292         dram_offline_data_flags = ERR_MAGIC_NUMBER;
2293         goto exit;
2294     }
2295
2296     ret = blkdev_read(bootdev, part_dram_data_addr + ((unsigned long) &datap->mrr_info), sizeof(mrr_info), (u8*)&mrr_info, PART_ID_DRAM_DATA);
2297     if (ret != 0) {
2298         dramc_crit("[dramc] blkdev_read %s failed\n", "data");
2299         dram_offline_data_flags = ERR_BLKDEV_READ_FAIL;
2300         goto exit;
2301     }
2302
2303     /* check checksum */
2304     if (check_checksum_for_mdl_data(&mrr_info) != 1) {
2305         dramc_crit("[dramc] checksum failed\n");
2306         dram_offline_data_flags = ERR_CHECKSUM;
2307
2308         goto exit;
2309     }
2310
2311     emi_checksum = crc16((u8*)emi_settings, sizeof(emi_settings));
2312
2313     if (emi_checksum != mrr_info.emi_checksum) {
2314         dramc_crit("[dramc] emi checksum failed\n");
2315         dram_offline_data_flags = ERR_CHECKSUM;
2316
2317         goto exit;
2318     }
2319
2320     /* copy the data stored in storage to the data structure for calibration */
2321     memcpy(DramInfo, &(mrr_info.DramInfo), sizeof(*DramInfo));
2322
2323 exit:
2324     if (dram_offline_data_flags)
2325         SET_DRAM_STORAGE_API_ERR(dram_offline_data_flags, DRAM_STORAGE_API_READ);
2326
2327     return 0 - dram_offline_data_flags;
2328 }

config

platform/ac8257/src/drivers/inc/dramc_pi_api.h

 363 // Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify
 364 #if (FOR_DV_SIMULATION_USED==0)
 365 // Preloader: using config CFG_DRAM_CALIB_OPTIMIZATION to identify
 366 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION       CFG_DRAM_CALIB_OPTIMIZATION
 367 #else
 368 // DV simulation, use full calibration flow
 369 #define SUPPORT_SAVE_TIME_FOR_CALIBRATION       0
 370 #endif

platform/ac8257/default.mak

 19 # DRAM Calibration Optimization:
 20 # DRAM calib data will be stored to storage device to enhance DRAM init speed.
 21 CFG_DRAM_CALIB_OPTIMIZATION :=1

ddr_info

# cat /proc/ddr_info
ddr_info:     0x213
DRAM density: 2048 MB
vendor ID:    0x13

DRAM_TYPE

 780 typedef enum
 781 {
 782     TYPE_DDR1 = 1,
 783     TYPE_LPDDR2,
 784     TYPE_LPDDR3,
 785     TYPE_PCDDR3,
 786     TYPE_LPDDR4,
 787     TYPE_LPDDR4X,
 788     TYPE_LPDDR4P
 789 } DRAM_DRAM_TYPE_T;

LPDDR4X

platform/ac8257/src/drivers/mt_vcore.c
platform/ac8257/src/drivers/dramc_pi_main.c
platform/ac8257/src/drivers/dramc_pi_calibration_api.c
platform/ac8257/src/drivers/emi.c
platform/ac8257/src/drivers/dramc_pi_basic_api.c

使用LPDDR4X时，不能限制最高速度为DDR2400？

1696 #ifdef MTK_LP4_HIGHEST_DDR2400
1697     if (mt_get_dram_type_from_hw_trap() == TYPE_LPDDR4X) {
1698         dramc_crit("[DRAMC] detect MTK_LP4_HIGHEST_DDR2400 for LP4X\n");
1699         ASSERT(0);
1700     }
1701 #else
1702     if (mt_get_dram_type_from_hw_trap() == TYPE_LPDDR4) {
1703         dramc_crit("[DRAMC] no MTK_LP4_HIGHEST_DDR2400 for LP4\n");
1704         ASSERT(0);
1705     }
1706 #endif

LPDDR4

custom/ac8257_demo_1g_32/ac8257_demo_1g_32.mk

MTK_LP4_HIGHEST_DDR2400=yes

mt6357

mreg_dbg_print

platform/ac8257/src/drivers/inc/ac8257.h

210 #if AC8257_DEBUG
211 #define PMUTAG                "[AC8257] "
212 #define mreg_dbg_print(fmt, arg...) dbg_print(PMUTAG fmt, ##arg)
213 #else
214 #define mreg_dbg_print(...) do { } while(0)
215 #endif

platform/ac8257/src/drivers/ac8257.c

mreg_dbg_print("
1	ac8257_set_voltage
2	ac8257_enable
3	ac8257_is_enabled
4	ac8257_set_mode
5	ac8257_get_mode
6	ac8257_set_votrim
7	ac8257_get_votrim

id

 61 static struct ac8257_regulator_info ac8257_regu_info[] = {
 62     ac8257_decl(vs1),
 63     ac8257_decl(vmodem),
 64     ac8257_decl(vcore),
 65     ac8257_decl(vproc),
 66     ac8257_decl(vpa),
 67     ac8257_decl(vsram_others),
 68     ac8257_decl(vsram_proc),
 69 #ifdef LDO_SUPPORT
 70     ac8257_decl(vdram),
 71 #endif /*--LDO_SUPPORT--*/
 72 };

id
0	vs1
1	vmodem
2	vcore
3	vproc
4	vpa
5	vsram_others
6	vsram_proc
7	vdram

log

latch VPROC 800000 uV
latch VSRAM_PROC 1068750 uV
latch VSRAM_OTHERS 900000 uV
latch VCORE 800000 uV
latch VMODEM 800000 uV

[AC8257] 1 6,61
[AC8257] 1 2,45
[AC8257] 1 1,48
[AC8257] get volt 5, 61, 900000
vsram_others = 900000 uV
[AC8257] get volt 3, 45, 800000
vproc = 800000 uV
[AC8257] get volt 6, 61, 900000
vsram_proc = 900000 uV
[AC8257] get volt 2, 45, 800000
vcore = 800000 uV
[AC8257] get volt 1, 48, 800000
vmodem = 800000 uV
[AC8257] 2 6,1
[AC8257] 2 5,1
[AC8257] 2 3,1
[AC8257] 2 2,1
[AC8257] 2 1,1

[AC8257] 4 2,1
[AC8257] 2 7,0
enable RT5738_VDD2 fail (ret = 0)

[AC8257] 1 2,25
Read voltage for 800
Vio18 = 1790000
[AC8257] get volt 2, 25, 675000
Vcore = 675000
Vdram = 0
[AC8257] 1 2,37
Read voltage for 1200
Vio18 = 1790000
[AC8257] get volt 2, 37, 750000
Vcore = 750000
Vdram = 0
[AC8257] 1 2,37
Read voltage for 1200
Vio18 = 1790000
[AC8257] get volt 2, 37, 750000
Vcore = 750000
Vdram = 0
[AC8257] 4 2,0
[AC8257] 1 2,45
[AC8257] get volt 2, 45, 800000
Vcore = 800000

ac8257_get_voltage

122 static int ac8257_get_voltage(unsigned char id)
123 {
124     unsigned int selector = 0;
125     unsigned int volt = 0;
126     int ret = 0;
127
128 #ifndef CFG_MTK_TINYSYS_SSPM_SUPPORT
129     unsigned int step_uV = step_uv[(ac8257_regu_info[id].vtype)];
130     unsigned short vol_shift = vo_shift[(ac8257_regu_info[id].vspos)];
131     unsigned short vol_mask = vo_mask[(ac8257_regu_info[id].vmpos)];
132 #endif /*--NON SSPM MODE--*/
133
134     ret = pmic_read_interface(ac8257_regu_info[id].vol_reg, &selector, vol_mask, vol_shift);
135     if (ret)
136         return -1;
137
138     if (ac8257_regu_info[id].rtype == REGULAR_VOLTAGE)
139         volt = ((selector * step_uV) + ac8257_regu_info[id].min_uV);
140 #ifdef LDO_SUPPORT
141     else if (ac8257_regu_info[id].rtype == NON_REGULAR_VOLTAGE)
142         volt = ac8257_ldo_convert_data(id, selector, SELTOVOL);
143     else if (ac8257_regu_info[id].rtype == FIXED_REGULAR_VOLTAGE) {
144         volt = *((int *)(ac8257_regu_info[id].extinfo->pvoltages));
145     }
146 #else
147     else
148         return -1;
149 #endif /*--LDO_SUPPORT--*/
150
151     mreg_dbg_print("get volt %d, %d, %d\n", id, selector, volt);
152     if (volt > ac8257_regu_info[id].max_uV || volt < ac8257_regu_info[id].min_uV) {
153         mreg_dbg_print("vgw\n");
154         return -1;
155     }
156
157     return volt;
158 }