Qemu-STM32(八)：STM32F407加入Timer控制器

已于 2025-03-05 08:51:47 修改
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分类专栏： qemu 文章标签： stm32 嵌入式硬件 单片机
于 2025-02-27 01:46:11 首次发布
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本文链接：https://blog.youkuaiyun.com/yanl1229/article/details/145892507
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概述

本文主要描述了在Qemu平台中，如何添加STM32F407的Timer控制器模拟代码。

参考资料

STM32F4XX TRM手册，手册编号：RM0090

添加步骤

1、在hw/arm/Kconfig文件中添加STM32F4XX_TIMER，如下所示:

+号部分为新增加内容

--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -341,6 +341,7 @@ config STM32F407_SOC
     select STM32F4XX_USART
     select STM32F4XX_RCC
     select STM32F4XX_PWR
+    select STM32F4XX_TIMER

2、在include/hw/arm/stm32f407_soc.h文件中添加

+号部分为新增加内容

--- a/include/hw/arm/stm32f407_soc.h
+++ b/include/hw/arm/stm32f407_soc.h
@@ -28,6 +28,7 @@
 #include "hw/char/stm32f4xx_usart.h"
 #include "hw/misc/stm32f4xx_rcc.h"
 #include "hw/misc/stm32f4xx_pwr.h"
+#include "hw/timer/stm32f4xx_timer.h"
 
 #define TYPE_STM32F407_SOC "stm32f407-soc"
 #define STM32F407_SOC(obj) \
@@ -43,7 +44,21 @@
 #define STM32F407_USART2    0x40004400
 #define STM32F407_USART3    0x40004800
 #define STM32F407_USART6    0x40011400
-
+#define STM_NUM_TIMERS      4
+#define STM32F407_TIM1      0x40010000
+#define STM32F407_TIM2      0x40000000
+#define STM32F407_TIM3      0x40000400
+#define STM32F407_TIM4      0x40000800
+#define STM32F407_TIM5      0x40000c00
+#define STM32F407_TIM6      0x40001000
+#define STM32F407_TIM7      0x40001400
+#define STM32F407_TIM8      0x40010400
+#define STM32F407_TIM9      0x40014000
+#define STM32F407_TIM10     0x40014400
+#define STM32F407_TIM11     0x40014800
+#define STM32F407_TIM12     0x40001800
+#define STM32F407_TIM13     0x40001c00
+#define STM32F407_TIM14     0x40002000
 #define RCC_BASE_ADDR       0x40023800
 #define POWER_BASE_ADDR     0x40007000
 
@@ -68,6 +83,7 @@ typedef struct STM32F407State {
     STM32F4XXRccState rcc;
     STM32F4XXPowerState power;
     STM32F4XXUsartState usart[STM_NUM_USARTS];
+    STM32F4XXTimerState timer[STM_NUM_TIMERS];
 } STM32F407State;

3、在hw/arm/stm32f407_soc.c文件中添加如下代码片段

+号部分为新增加内容

--- a/hw/arm/stm32f407_soc.c
+++ b/hw/arm/stm32f407_soc.c
@@ -32,6 +32,11 @@
 #include "hw/arm/stm32f407_soc.h"
 #include "sysemu/sysemu.h"
 
+static const uint32_t timer_addr[STM_NUM_TIMERS] = {
+    STM32F407_TIM2, STM32F407_TIM3, STM32F407_TIM4,
+    STM32F407_TIM5
+};
+
 static const uint32_t usart_addr[STM_NUM_USARTS] = {
     STM32F407_USART1, STM32F407_USART2, STM32F407_USART3,
     STM32F407_USART6
@@ -47,6 +52,10 @@ static const int exti_irq[] =
     40, 40, 40, 40, 40
 };
 
+static const int timer_irq[STM_NUM_TIMERS] = {
+    28, 29, 30, 50
+};
+
 static void stm32f407_soc_initfn(Object *obj)
 {
 
@@ -70,6 +79,11 @@ static void stm32f407_soc_initfn(Object *obj)
         object_initialize(&s->usart[i], sizeof(s->usart[i]), TYPE_STM32F4XX_USART);
         qdev_set_parent_bus(DEVICE(&s->usart[i]), sysbus_get_default());
     }
+
+    for (i = 0; i < STM_NUM_TIMERS; i++) {
+        object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_STM32F4XX_TIMER);
+        qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default());
+    }
 }
 
 static void stm32f407_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -147,6 +161,19 @@ static void stm32f407_soc_realize(DeviceState *dev_soc, Error **errp)
         sysbus_mmio_map(busdev, 0, usart_addr[i]);
         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
     }
+    /* Timer 2 to 5 contoller */
+    for (i = 0; i < STM_NUM_TIMERS; i++) {
+        dev = DEVICE(&(s->timer[i]));
+        qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
+        object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
+        if (err != NULL) {
+            error_propagate(errp, err);
+            return;
+        }
+        busdev = SYS_BUS_DEVICE(dev);
+        sysbus_mmio_map(busdev, 0, timer_addr[i]);
+        sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
+    }
 }

4.在hw/timer/Kconfig中添加

--- a/hw/timer/Kconfig
+++ b/hw/timer/Kconfig
@@ -28,6 +28,9 @@ config ALLWINNER_A10_PIT
 config STM32F2XX_TIMER
     bool
 
+config STM32F4XX_TIMER
+    bool
+
 config CMSDK_APB_TIMER
     bool
     select PTIMER

5.在hw/timer/Makefile.objs中添加

--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -29,6 +29,7 @@ common-obj-$(CONFIG_MIPS_CPS) += mips_gictimer.o
 common-obj-$(CONFIG_ALLWINNER_A10_PIT) += allwinner-a10-pit.o
 
 common-obj-$(CONFIG_STM32F2XX_TIMER) += stm32f2xx_timer.o
+common-obj-$(CONFIG_STM32F4XX_TIMER) += stm32f4xx_timer.o
 common-obj-$(CONFIG_ASPEED_SOC) += aspeed_timer.o
 
 common-obj-$(CONFIG_CMSDK_APB_TIMER) += cmsdk-apb-timer.o

6.在hw/timer/创建新文件stm32f4xx_timer.c

--- /dev/null
+++ b/hw/timer/stm32f4xx_timer.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2020 liang yan <yanl1229@163.com>
+ *
+ * STM32F4XX Timer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#include "qemu/osdep.h"
+#include "hw/timer/stm32f4xx_timer.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qemu/module.h"
+#include "migration/vmstate.h"
+
+#ifndef STM_TIMER_ERR_DEBUG
+#define STM_TIMER_ERR_DEBUG 0
+#endif
+
+#define DB_PRINT_L(lvl, fmt, args...) do { \
+    if (STM_TIMER_ERR_DEBUG >= lvl) { \
+        qemu_log("%s: " fmt, __func__, ## args); \
+    } \
+} while (0);
+
+#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
+
+static void stm32f4xx_timer_set_alarm(STM32F4XXTimerState *s, int64_t now);
+
+static void stm32f4xx_timer_interrupt(void *opaque)
+{
+    STM32F4XXTimerState *s = opaque;
+
+    DB_PRINT("Interrupt\n");
+
+    if (s->tim_dier & (TIM_DIER_UIE|TIM_DIER_CC1IE|TIM_DIER_CC2IE|TIM_DIER_CC3IE|TIM_DIER_CC4IE)
+        && s->tim_cr1 & TIM_CR1_CEN) {
+        if (!(s->tim_cr1 & TIM_CR1_URS)) {
+            s->tim_sr |= TIM_SR_UIF;
+            qemu_irq_pulse(s->irq);
+        }
+        stm32f4xx_timer_set_alarm(s, s->hit_time);
+    }
+
+    if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) &&
+        !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) &&
+        s->tim_ccmr1 & TIM_CCMR1_OC2PE &&
+        s->tim_ccer & TIM_CCER_CC2E) {
+        /* PWM 2 - Mode 1 */
+        DB_PRINT("PWM2 Duty Cycle: %d%%\n",
+                s->tim_ccr2 / (100 * (s->tim_psc + 1)));
+    }
+}
+
+static inline int64_t stm32f4xx_ns_to_ticks(STM32F4XXTimerState *s, int64_t t)
+{
+    return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1);
+}
+
+static void stm32f4xx_timer_set_alarm(STM32F4XXTimerState *s, int64_t now)
+{
+    uint64_t ticks;
+    int64_t now_ticks;
+
+    if (s->tim_arr == 0) {
+        return;
+    }
+
+    DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1);
+
+    now_ticks = stm32f4xx_ns_to_ticks(s, now);
+    if (!(s->tim_cr1 & TIM_CR1_CMS))
+        s->tim_arr = s->tim_arr - 1;
+    ticks = s->tim_arr - (now_ticks - s->tick_offset);
+
+    DB_PRINT("Alarm set in %d ticks\n", (int) ticks);
+
+    s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1),
+                               1000000000ULL, s->freq_hz);
+
+    timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time);
+    DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time);
+}
+
+static void stm32f4xx_timer_reset(DeviceState *dev)
+{
+    STM32F4XXTimerState *s = STM32F4XXTIMER(dev);
+    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+
+    s->tim_cr1 = 0;
+    s->tim_cr2 = 0;
+    s->tim_smcr = 0;
+    s->tim_dier = 0;
+    s->tim_sr = 0;
+    s->tim_egr = 0;
+    s->tim_ccmr1 = 0;
+    s->tim_ccmr2 = 0;
+    s->tim_ccer = 0;
+    s->tim_cnt = 0;
+    s->tim_psc = 0;
+    s->tim_arr = 0;
+    s->tim_ccr1 = 0;
+    s->tim_ccr2 = 0;
+    s->tim_ccr3 = 0;
+    s->tim_ccr4 = 0;
+    s->tim_dcr = 0;
+    s->tim_dmar = 0;
+    s->tim_or = 0;
+
+    s->tick_offset = stm32f4xx_ns_to_ticks(s, now);
+}
+
+static uint64_t stm32f4xx_timer_read(void *opaque, hwaddr offset,
+                           unsigned size)
+{
+    STM32F4XXTimerState *s = opaque;
+
+    DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset);
+
+    switch (offset) {
+    case TIM_CR1:
+        return s->tim_cr1;
+    case TIM_CR2:
+        return s->tim_cr2;
+    case TIM_SMCR:
+        return s->tim_smcr;
+    case TIM_DIER:
+        return s->tim_dier;
+    case TIM_SR:
+        return s->tim_sr;
+    case TIM_EGR:
+        return s->tim_egr;
+    case TIM_CCMR1:
+        return s->tim_ccmr1;
+    case TIM_CCMR2:
+        return s->tim_ccmr2;
+    case TIM_CCER:
+        return s->tim_ccer;
+    case TIM_CNT:
+        return stm32f4xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) -
+               s->tick_offset;
+    case TIM_PSC:
+        return s->tim_psc;
+    case TIM_ARR:
+        return s->tim_arr;
+    case TIM_CCR1:
+        return s->tim_ccr1;
+    case TIM_CCR2:
+        return s->tim_ccr2;
+    case TIM_CCR3:
+        return s->tim_ccr3;
+    case TIM_CCR4:
+        return s->tim_ccr4;
+    case TIM_DCR:
+        return s->tim_dcr;
+    case TIM_DMAR:
+        return s->tim_dmar;
+    case TIM_OR:
+        return s->tim_or;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
+    }
+
+    return 0;
+}
+
+static void stm32f4xx_timer_write(void *opaque, hwaddr offset,
+                        uint64_t val64, unsigned size)
+{
+    STM32F4XXTimerState *s = opaque;
+    uint32_t value = val64;
+    int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+    uint32_t timer_val = 0;
+
+    DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset);
+
+    switch (offset) {
+    case TIM_CR1:
+        s->tim_cr1 |= value;
+        if (s->tim_cr1 & TIM_CR1_CEN)
+            stm32f4xx_timer_set_alarm(s, now);
+        if ((value & TIM_CR1_DIR) && ((s->tim_cr1 & TIM_CR1_CMS)))
+            s->tim_cr1 |= TIM_CR1_DIR;
+        break;
+    case TIM_CR2:
+        s->tim_cr2 |= value;
+        break;
+    case TIM_SMCR:
+        s->tim_smcr |= value;
+        break;
+    case TIM_DIER:
+        s->tim_dier |= value;
+        break;
+    case TIM_SR:
+        /* This is set by hardware and cleared by software */
+        s->tim_sr &= value;
+        break;
+    case TIM_EGR:
+        s->tim_egr = value;
+        /* software generate Update event */
+        if (s->tim_egr & TIM_EGR_UG) {
+            s->tick_offset = stm32f4xx_ns_to_ticks(s, now);
+            if (s->tim_cr1 & TIM_CR1_CEN)
+                stm32f4xx_timer_set_alarm(s, now);
+        }
+        break;
+    case TIM_CCMR1:
+        s->tim_ccmr1 |= value;
+        break;
+    case TIM_CCMR2:
+        s->tim_ccmr2 |= value;
+        break;
+    case TIM_CCER:
+        s->tim_ccer |= value;
+        break;
+    case TIM_PSC:
+        timer_val = stm32f4xx_ns_to_ticks(s, now) - s->tick_offset;
+        s->tim_psc |= value & 0xFFFF;
+        s->tick_offset = stm32f4xx_ns_to_ticks(s, now) - timer_val;
+        if (s->tim_cr1 & TIM_CR1_CEN)
+            stm32f4xx_timer_set_alarm(s, now);
+        break;
+    case TIM_CNT:
+        timer_val |= value;
+        break;
+    case TIM_ARR:
+        s->tim_arr |= value;
+        break;
+    case TIM_CCR1:
+        s->tim_ccr1 |= value;
+        break;
+    case TIM_CCR2:
+        s->tim_ccr2 |= value;
+        break;
+    case TIM_CCR3:
+        s->tim_ccr3 |= value;
+        break;
+    case TIM_CCR4:
+        s->tim_ccr4 |= value;
+        break;
+    case TIM_DCR:
+        s->tim_dcr |= value;
+        break;
+    case TIM_DMAR:
+        s->tim_dmar |= value;
+        break;
+    case TIM_OR:
+        s->tim_or |= value;
+        break;
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset);
+        break;
+    }
+}
+
+static const MemoryRegionOps stm32f4xx_timer_ops = {
+    .read = stm32f4xx_timer_read,
+    .write = stm32f4xx_timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_stm32f4xx_timer = {
+    .name = TYPE_STM32F4XX_TIMER,
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_INT64(tick_offset, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_cr1, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_cr2, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_smcr, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_dier, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_sr, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_egr, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccmr1, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccmr2, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccer, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_psc, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_arr, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccr1, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccr2, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccr3, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_ccr4, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_dcr, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_dmar, STM32F4XXTimerState),
+        VMSTATE_UINT32(tim_or, STM32F4XXTimerState),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static Property stm32f4xx_timer_properties[] = {
+    DEFINE_PROP_UINT64("clock-frequency", struct STM32F4XXTimerState,
+                       freq_hz, 1000000000),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void stm32f4xx_timer_init(Object *obj)
+{
+    STM32F4XXTimerState *s = STM32F4XXTIMER(obj);
+
+    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
+
+    memory_region_init_io(&s->iomem, obj, &stm32f4xx_timer_ops, s,
+                          "stm32f4xx_timer", 0x400);
+    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
+
+    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f4xx_timer_interrupt, s);
+}
+
+static void stm32f4xx_timer_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = stm32f4xx_timer_reset;
+    device_class_set_props(dc, stm32f4xx_timer_properties);
+    dc->vmsd = &vmstate_stm32f4xx_timer;
+}
+
+static const TypeInfo stm32f4xx_timer_info = {
+    .name          = TYPE_STM32F4XX_TIMER,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(STM32F4XXTimerState),
+    .instance_init = stm32f4xx_timer_init,
+    .class_init    = stm32f4xx_timer_class_init,
+};
+
+static void stm32f4xx_timer_register_types(void)
+{
+    type_register_static(&stm32f4xx_timer_info);
+}
+
+type_init(stm32f4xx_timer_register_types)

7.在include/hw/timer/创建stm32f4xx_timer.h文件

--- /dev/null
+++ b/include/hw/timer/stm32f4xx_timer.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2020 liang yan <yanl1229@163.com>
+ *
+ * STM32F4XX Timer
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+#ifndef HW_STM32F4XX_TIMER_H
+#define HW_STM32F4XX_TIMER_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+
+#define TIM_CR1      0x00
+#define TIM_CR2      0x04
+#define TIM_SMCR     0x08
+#define TIM_DIER     0x0C
+#define TIM_SR       0x10
+#define TIM_EGR      0x14
+#define TIM_CCMR1    0x18
+#define TIM_CCMR2    0x1C
+#define TIM_CCER     0x20
+#define TIM_CNT      0x24
+#define TIM_PSC      0x28
+#define TIM_ARR      0x2C
+#define TIM_CCR1     0x34
+#define TIM_CCR2     0x38
+#define TIM_CCR3     0x3C
+#define TIM_CCR4     0x40
+#define TIM_DCR      0x48
+#define TIM_DMAR     0x4C
+#define TIM_OR       0x50
+
+#define TIM_CR1_CEN   (1 << 0)
+#define TIM_CR1_URS   (1 << 2)
+#define TIM_CR1_CMS   (3 << 6)
+#define TIM_CR1_DIR   (1 << 4)
+
+#define TIM_EGR_UG 1
+
+#define TIM_CCER_CC2E   (1 << 4)
+#define TIM_CCMR1_OC2M2 (1 << 14)
+#define TIM_CCMR1_OC2M1 (1 << 13)
+#define TIM_CCMR1_OC2M0 (1 << 12)
+#define TIM_CCMR1_OC2PE (1 << 11)
+
+#define TIM_DIER_UIE    (1 << 0)
+#define TIM_DIER_CC1IE  (1 << 1)
+#define TIM_DIER_CC2IE  (1 << 2)
+#define TIM_DIER_CC3IE  (1 << 3)
+#define TIM_DIER_CC4IE  (1 << 4)
+
+#define TIM_SR_UIF      (1 << 0)
+
+#define TYPE_STM32F4XX_TIMER "stm32f4xx-timer"
+#define STM32F4XXTIMER(obj) OBJECT_CHECK(STM32F4XXTimerState, \
+                            (obj), TYPE_STM32F4XX_TIMER)
+
+typedef struct STM32F4XXTimerState {
+    /* <private> */
+    SysBusDevice parent_obj;
+
+    /* <public> */
+    MemoryRegion iomem;
+    QEMUTimer *timer;
+    qemu_irq irq;
+
+    int64_t tick_offset;
+    uint64_t hit_time;
+    uint64_t freq_hz;
+
+    uint32_t tim_cr1;
+    uint32_t tim_cr2;
+    uint32_t tim_smcr;
+    uint32_t tim_dier;
+    uint32_t tim_sr;
+    uint32_t tim_egr;
+    uint32_t tim_ccmr1;
+    uint32_t tim_ccmr2;
+    uint32_t tim_ccer;
+    uint32_t tim_cnt;
+    uint32_t tim_psc;
+    uint32_t tim_arr;
+    uint32_t tim_ccr1;
+    uint32_t tim_ccr2;
+    uint32_t tim_ccr3;
+    uint32_t tim_ccr4;
+    uint32_t tim_dcr;
+    uint32_t tim_dmar;
+    uint32_t tim_or;
+} STM32F4XXTimerState;
+
+#endif

总结

1、本文描述了如何在qemu中添加stm32f407平台上Timer控制器实现；

2、完成的提交记录，请查看代码库链接;

链接：

1、qemu代码库链接

yanl1229/qemu-5.0

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