最近整理的一些msm8909平台英文文档4 - i2c_function_of_msm8909

本文介绍了如何在MSM8909平台上配置QUP核心作为I2C设备的方法,包括创建设备树节点、设置时钟、配置GPIO等步骤,并提供了快速验证I2C总线是否正常工作的指导。

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Introduction
The QUP provides a general purpose data path engine support multiple mini cores. Each minicore implements protocol-specific logic. The common FIFOs provide a consistent system IO and system DMA model across widely varying external interface types. For example, one pair of FIFO can support SPI and I2C MiniCores independently.

Currently supported MiniCores
SPI
I2C

I2C Core:
Support I2C Standard (100 kHz), and Fast (400 kHz)
Key features added for MSM8909:
BAM integration
Support TAG (version 2)

QUP base address for QUPs:
In order to match the labeling of software interface manual, each QUP will be identified by BLSP core and QUP core (0 - 5). In hardware design documents, BLSPs are identified as BLSP[1:6]

BLSP hardware ID QUP core physical address (QUP_BASE_ADDRESS):
BLSP BLSP     1  QUP 0    0x78B5000
BLSP BLSP     1  QUP 1    0x78B6000
BLSP BLSP     1  QUP 2    0x78B7000
BLSP BLSP     1  QUP 3    0x78B8000
BLSP BLSP     1  QUP 4    0x78B9000
BLSP BLSP     1  QUP 5    0x78BA000

IRQs for QUPs:
BLSP BLSP 1 QUP 0 95
BLSP BLSP 1 QUP 1 96
BLSP BLSP 1 QUP 2 97
BLSP BLSP 1 QUP 3 98
BLSP BLSP 1 QUP 4 99
BLSP BLSP 1 QUP 5 100

Configure QUP core as I2C in kernel
This section describes steps necessary to configure any of the six QUP cores available in MSM8909 to configure and use as a I2C device. By default QTI already preconfigures BLSP1_QUP5 as I2C.

See kernel/arch/arm/boot/dts/qcom/sim8909_evb103-msm8909.dtsi for more details. Following example shows how to configure BLSP1_QUP0 as I2C.

1. Create device tree node:
User can use kernel/arch/arm/boot/sim8909_evb103-msm8909.dtsi

	i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr";
		reg = <0x78b5000 0x1000>;
		interrupt-names = "qup_irq";
		interrupts = <0 95 0>;
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
		         <&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
		clock-names = "iface_clk", "core_clk";
		qcom,clk-freq-out = <100000>;
		qcom,clk-freq-in  = <19200000>;
		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_1_active>;
		pinctrl-1 = <&i2c_1_sleep>;
		qcom,noise-rjct-scl = <0>;
		qcom,noise-rjct-sda = <0>;
		dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
			<&dma_blsp1 5  32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
	};

For latest detail plese follow :
kernel/Documentation/devicetree/bindings/i2c/i2c-qup.txt

Set up clocks:
kernel/drivers/clk/qcom/clock-gcc-8909.c

static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
	.cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
	.has_sibling = 0,
	.base = &virt_bases[GCC_BASE],
	.c = {
		.dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
		.parent = &blsp1_qup1_i2c_apps_clk_src.c,
		.ops = &clk_ops_branch,
		CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
	},
};

static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
	.cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
	.set_rate = set_rate_hid,
	.freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
	.current_freq = &rcg_dummy_freq,
	.base = &virt_bases[GCC_BASE],
	.c = {
		.dbg_name = "blsp1_qup1_i2c_apps_clk_src",
		.ops = &clk_ops_rcg,
		VDD_DIG_FMAX_MAP1(LOWER, 50000000),
		CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
	},
};

2. Setup GPIOs:
kernel/arch/arm/boot/sim8909_evb103-msm8909-pinctrl.dtsi

pmx_i2c_1 {
                        /* CLK, DATA */
			qcom,pins = <&gp 6>, <&gp 7>;
			qcom,num-grp-pins = <2>;
			qcom,pin-func = <3>;
			label = "pmx_i2c_1";


			i2c_1_active: i2c_1_active {
				drive-strength = <2>; /* 2 MA */
				bias-disable = <0>; /* No PULL */
			};


			i2c_1_sleep: i2c_1_sleep {
				drive-strength = <2>; /* 2 MA */
				bias-pull-down; /* PULL DOWN */
			};
		};


Quick verification:
This section describes how to quickly verify I2C bus.
Check if the bus is registered. If you have entered all the information correctly, then you should see I2C bus.
registered under /dev/i2c-#. Where cell-index would match the bus #.
adb shell --> Get adb shell
cd /dev/
ls i2c* --> to List all the I2C buses

For example:
root@android:/dev # ls i2c*
ls i2c*
i2c-0

i2c-1




### msm8909 GPIO94 Configuration and Usage in Qualcomm Platform For the Qualcomm MSM8909 platform, configuring a specific General-Purpose Input/Output (GPIO) such as GPIO94 involves understanding both hardware connections and software settings within the device tree or kernel source code. In the context of configuring GPIOs on an MSM8909 chipset-based system, one typically needs to modify the Device Tree Source (DTS) files that define how peripherals are connected at boot time. The DTS file for this particular SoC would contain entries specifying what function each pin serves when not used by default components like UART, SPI, I2C, etc.[^1] To configure GPIO94 specifically: - **Pin Multiplexing**: Ensure that GPIO94 is set up correctly through pinmux configurations which can be adjusted via the DTS file. ```c gpio94 { pinctrl-names = "default"; pinctrl-0 = <&gpio94_default>; status = "okay"; }; ``` - **Setting Direction and Value**: Once properly multiplexed into GPIO mode, setting its direction (input/output) and value could occur either from userspace applications using sysfs interface or directly inside drivers during initialization stages. Regarding practical application scenarios involving Bluetooth modules similar to BTS4025 mentioned earlier, it might involve controlling power rails or reset lines associated with external chips over certain GPIO pins including possibly GPIO94 depending upon board design specifics. Additionally, while commands related to camera settings adjustments have been noted[^2], these do not directly relate to GPIO management but illustrate different aspects of tuning Android devices running on Qualcomm platforms where various functionalities interact closely together under Linux-based operating systems. Lastly, regarding sleep events and their placeholders[^3], although indirectly linked due to potential interactions between low-power states and peripheral control mechanisms managed partly through GPIO interfaces, direct correlation here remains less explicit compared to other areas discussed above. --related questions-- 1. How does modifying the DTS impact overall functionality? 2. What tools exist for debugging issues arising after changing GPIO configurations? 3. Can you provide examples of common mistakes made when altering GPIO setups? 4. In what ways do changes to GPIO affect battery life?
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