vhdl实现寄存器的代码（生成的元件更少）

VHDL实现精简寄存器代码

最新推荐文章于 2023-05-25 11:23:45 发布

原创

最新推荐文章于 2023-05-25 11:23:45 发布 · 1.5k 阅读

1 ·

CC 4.0 BY-SA版权

文章标签：

#vector #primitive #library

本文档提供了一段使用VHDL语言实现的寄存器代码，通过库IEEE.STD_LOGIC_1164, IEEE.STD_LOGIC_ARITH和IEEE.STD_LOGIC_UNSIGNED，创建了一个带有输入输出接口的寄存器组件。当使能信号cs和写入信号wr为高时，数据被写入寄存器；当cs和读取信号rd为高时，数据从寄存器中读出。在非活动状态下，数据端口默认为"ZZZZ"。" 128767166,11222196,OP-TEE实战：TA与CA调试与应用解析,"['系统安全', 'TEEOS', 'TA', 'CA']

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exprience1 is
    Port ( cs : in std_logic;
           wr : in std_logic;
           rd : in std_logic;
           data : inout std_logic_vector(3 downto 0)
             --signal tmp: inout std_logic_vector(3 downto 0));
            );
end exprience1;

architecture Behavioral of exprience1 is
signal tmp: std_logic_vector(3 downto 0);
begin

p1:process(cs, wr)
begin
if(cs = '1'and wr = '1') then
tmp <=data;
else data <= "ZZZZ";
end if;
end process p1;

p2:process(cs,rd)
begin
if(cs = '1' and rd = '1') then
data <= tmp;
else data <= "ZZZZ";
end if;
end process p2;

end Behavioral;

;