CORDIC IP核

输出sin波形

cordicIP核配置：

 testbench:

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2025/01/01 19:36:54
// Design Name: 
// Module Name: tb_cordic
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module tb_cordic(
    
    );
    reg aclk =1'd0;
    reg s_axis_phase_tvalid = 1'd1;
    reg [15:0] s_axis_phase_tdata = 1'd0;
    wire m_axis_dout_tvalid;
    wire [31:0]m_axis_dout_tdata;
    
    always #1 aclk =~aclk;
    always @(posedge aclk)
    if(s_axis_phase_tdata == 16'h2000)
        s_axis_phase_tdata <&#