<?xml version="1.0" encoding="utf-8" ?><rss version="2.0"><channel><title><![CDATA[nomorepolishing的博客]]></title><description><![CDATA[]]></description><link>https://blog.youkuaiyun.com/weixin_58778901</link><language>zh-cn</language><generator>https://blog.youkuaiyun.com/</generator><copyright><![CDATA[Copyright &copy; weixin_58778901]]></copyright><item><title><![CDATA[More Verilog Features]]></title><link>https://blog.youkuaiyun.com/weixin_58778901/article/details/122147933</link><guid>https://blog.youkuaiyun.com/weixin_58778901/article/details/122147933</guid><author>weixin_58778901</author><pubDate>Sat, 25 Dec 2021 22:36:03 +0800</pubDate><description><![CDATA[Conditional ternary operators三目运算符


(Condition?) if_ture: if_false;



题目描述：比较四位无符号数a，b，c，d的大小，注意位宽为8。



module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);//

    wire  interm1;                             //运行错误原因在这儿
    wire  inter.]]></description><category></category></item><item><title><![CDATA[Procedures]]></title><link>https://blog.youkuaiyun.com/weixin_58778901/article/details/122116193</link><guid>https://blog.youkuaiyun.com/weixin_58778901/article/details/122116193</guid><author>weixin_58778901</author><pubDate>Thu, 23 Dec 2021 22:31:39 +0800</pubDate><description><![CDATA[Always blocks(combinational)-Alwaysblock1


题目描述：分别用assign连续赋值和always过程块描述 逻辑与门


A note on wire vs. reg:


The left-hand-side of an assign statement must be a net type (e.g., wire), while the left-hand-side of a procedural assignment (in an always block).]]></description><category></category></item><item><title><![CDATA[HDLBits 答案汇总（持续更新）]]></title><link>https://blog.youkuaiyun.com/weixin_58778901/article/details/122093785</link><guid>https://blog.youkuaiyun.com/weixin_58778901/article/details/122093785</guid><author>weixin_58778901</author><pubDate>Wed, 22 Dec 2021 19:57:40 +0800</pubDate><description><![CDATA[HDLBits solutions






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