26 CSRRS 与 CSRRW 与 CSRRCriscv指令 Tips

CSRRS 与 CSRRW 与 CSRRCriscv指令 详解

参考riscv指令集手册第76页

The CSRRS (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero- extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be set in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be set in the CSR, if that CSR bit is writable.
Other bits in the CSR are not explicitly written.
The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero- extends the value to XLEN bits, and writes it to integer register rd. The initial value in integer register rs1 is treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in rs1 will cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. Other bits in the CSR are not explicitly written.
For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal instruction exceptions on accesses to read-only CSRs. Both CSRRS and CSRRC always read the addressed CSR and cause any read side effects regardless of rs1 and rd fields. Note that if rs1 specifies a register holding a zero value other than x0, the instruction will still attempt to write the unmodified value back to the CSR and will cause any attendant side effects. A CSRRW with rs1=x0 will attempt to write zero to the destination CSR.

指令可以分为三种
1：带立即数的 CSRRWI 与 不带立即数的 CSRRW
2：带立即数的 CSRRS 与 不带立即数的 CSRRSI
3：带立即数的 CSRRC 与 不带立即数的 CSRRC

需要注意上述加粗字体，当rs1为 x0，就是当为gpr寄存器为第一个寄存器时，且指令为 CSRRS 或 CSRRC，此时csr中的值不发生改变。