HDLbits代码答案（2.4 Procedures & 2.5 More Verilog Features）持更

2. Verilog Language

2.3 Procedures

Procedures include always, initial, task, and function blocks. Procedures allow sequential statements (which cannot be used outside of a procedure) to be used to describe the behaviour of a circuit.
过程包括always、initial、task和function块。过程允许使用连续赋值语句(不能在过程之外使用)来描述电路行为。

• Combinational: always @(*)防止list遗漏，(In SystemVerilog, use always_comb.)

• Clocked: always @(posedge clk)

• assign左边必须是net类型(例如wire)；

• always块左边必须是变量类型(例如reg)。
  
  过程块内的语法和过程外的并不相同，过程块有更丰富的语句集(例如if-then, case)。

1. Always blocks (combinational) //用两种方式表达AND门

// synthesis verilog_input_version verilog_2001
module top_module(
    input a, 
    input b,
    output wire out_assign,
    output reg out_alwaysblock
);
    assign out_assign = a & b;
    
    always @(*) begin
        out_alwaysblock = a & b;
    end
       
endmodule

波形：

2. Always blocks (clocked) //3种方式表达XOR
阻塞与非阻塞赋值

• In a combinational always block, use blocking assignments. （=）
• In a clocked always block, use non-blocking assignments. （<=）
  

// synthesis verilog_input_version verilog_2001
module top_module(
    input clk,
    input a,
    input b,
    output wire out_assign,
    output reg out_always_comb,
    output reg out_always_ff   );

    assign out_assign = a ^ b;
    always @(*) out_always_comb = a ^ b;
    always @(posedge clk)
        out_always_ff <= a ^ b;
    
endmodule

3. If statement //2-1mux