AHB_Slave(SD_INTERFACE)部分代码 未完待续

 

AHB_SLAVE(SD_IF)部分代码如下：

module sd_if (
//-- ahb 
    input              hclk;
    input              hrst_n;
    input              hsl;
    input              hwrite;//1->write      0->read
    input       [1:0]  htrans; //4种 idel busy seq nonseq
    input       [2:0]  hburst;//8种 singal incr beat4/8/16 wrap4/8/16
    input  reg  [31:0] hwdata;//
    input       [31:0] haddr;
    input       [2:0]  hsize;//bus的宽度
    input              hready_in;//所有slave为高，hready_in才为高
    output             hready_out;//内部是否在忙，忙为0
    output      [1:0]  hresp;
    output      [31:0] hrdata;

//-- host_dma
    output reg         dma_en;
    output reg         dma_direc;//判断是从ahb->fifo还是从sd_fifo->ahb外部
    output reg  [15:0] transfer_size;//DMA这次搬多少
    output reg  [31:0] dma_addr;//若从外面搬，dma_addr是起始地址;往外面搬，dma_addr是目标地址。

    output reg         fifo_full_int_gen;
    output reg         fifo_empty_int_gen;
    output reg         dma_finish_int_gen;
    output reg         clr_fifo_full_int;
    output reg         clr_fifo_empty_int;
    output reg         clr_dma_finish_int;
    input              clr_dma_en;
    input              fifo_full_int;
    input              fifo_empty_int;
    input              dma_finish_int;

    input       [31:0] response0;//cmd给的response
    input       [31:0] response1;
    input       [31:0] response2;
    input       [31:0] response3;
    input              in_sd_clk;
    input              sd_fifo_empty;
    input              sd_fifo_full;
    input              sd_fifo_re;

    input              in_end_command;
    input              in_end_command_and_response;
    input              in_transfer_complete;
    input              in_send_data_crc_error;
    input              in_receive_data_crc_error;
    input              in_response_timeout;
    input              in_cmd_current_state;//当前cmd状态
    input              in_read_to_error;
    input              one_bk_re_end;
    output reg         sd_clk_enable;
    output reg         hw_stop_clk;
    output reg  [7:0]  sd_clk_divider;
    output reg         sd_soft_reset;
    output reg         high_speed_clk;
//  output reg         read_acce_option;
    output reg  [31:0] command_argument;
    output reg  [5:0]  command_index;
    output reg  [10:0] block_size;//需要发送多少个block
    output reg  [10:0] block_len;//一个block有多少byte
    output             sd_op_finish;
    output reg  [31:0] block_number;
    output reg         data_direction;
    output reg         data_width;
    output reg  [31:0] read_to;//read_timeout
    output             irq;
    output reg         out_response;//48bit
    output reg         out_longresponse;//136bit
    output reg         cmd_fsm_ready;
    output             data_fsm_ready;
);

    reg                hw_stop_clk_en;
    reg                command_enable;
    reg                data_present;
    reg         [1:0]  response_type;
    reg         [10:0] block_len_r;
    reg                read_to_error;
    reg                dma_finish_interrupt_mask;
    reg                end_command_and_response_interrupt_mask;
    reg                sd_fifo_empty_interrupt_mask;
    reg                fifo_full_interrpt_mask;
    reg                fifo_empty_interrupt_mask;
    reg                sd_fifo_full_interrupt_mask;
    reg                command_complete_interrupt_mask;
    reg                transfer_complete_interrupt_mask;
    reg                read_to_error_interrupt_mask;
    reg                rx_fifo_write_error_interrupt_mask;
    reg                tx_fifo_read_error_interrupt_mask;
    reg                read_data_crc_error_interrupt_mask;
    reg                write_data_crc_error_interrupt_mask;
    reg                response_timeout_error_interrupt_mask;

    reg                sd_fifo_empty_r;
    reg                       sd_fifo_full_r;
    reg                end_command;
    reg                transfer_complete;
    reg                 send_data_crc_error;
    reg                receive_data_crc_error;
    reg                response_timeout;              
    reg                end_command_and_response;

//-- internal register
    reg                hwrite_r;
    reg         [2:0]  hsize_r;
    reg         [2:0]  hburst_r;
    reg         [1:0]  htrans_r;
    reg         [31:0] haddr_r;

    reg                dma_end_tp;
    reg                dma_end;
    reg                dma_end_r;
    
    reg                cmd_ready_pre;

    reg         [31:0] block_number_ahb;
    reg         [31:0] block_num_tp;
    reg                one_bk_re_end_tp_1;
    reg                one_bk_re_end_tp_2;
    reg                one_bk_re_end_tp_3;
    reg                cmd_state_send_tp1;
    reg                cmd_state_send_tp2;
    reg                cmd_state_send_tp3;
    reg                in_end_cmd_and_resp_tp_1;
    reg                in_end_cmd_and_resp_tp_2;
    reg                in_end_cmd_and_resp_tp_3;
    reg                sd_fifo_empty_tp1;
    reg                in_end_cmd_tp_1;
    reg                in_end_cmd_tp_2;
    reg                in_end_cmd_tp_3;
    reg                in_transfer_end_tp_1;
    reg                in_transfer_end_tp_2;
    reg                in_transfer_end_tp_3;
    reg                in_rd_to_err_tp_1;
    reg                in_rd_to_err_tp_2;
    reg                in_rd_to_err_tp_3;
    reg                in_send_data_crc_err_tp_1;
    reg                in_send_data_crc_err_tp_2;
    reg                in_send_data_crc_err_tp_3;
    reg                in_receive_data_crc_err_tp_1;
    reg                in_receive_data_crc_err_tp_2;
    reg                in_receive_data_crc_err_tp_3;
    reg                in_resp_timeout_tp_1;
    reg                in_resp_timeout_tp_2;
    reg                in_resp_timeout_tp_3;
    reg         [31:0] response0_ahb;
    reg         [31:0] response1_ahb;
    reg         [31:0] response2_ahb;
    reg         [31:0] response3_ahb;
    wire               cmd_state_send;
    wire               ahb_wr_reg_en;
    wire               ahb_rd_reg_en;

// Generate AHB hready_out and hresp singals
// ------------------------------------------

assign hready_out = 1'b1;
assign hresp = 2'b0;

//------------------------------------------
// Register AHB bus control and Addr
// -----