Quartus Signal Tap II Debugging

最新推荐文章于 2025-01-02 14:49:38 发布

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最新推荐文章于 2025-01-02 14:49:38 发布

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分类专栏： FPGA 文章标签： fpga

本文链接：https://blog.youkuaiyun.com/weixin_40038116/article/details/107503195

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在Linux环境下使用Quartus Signal Tap II进行FPGA调试，包括打开RTL项目，设置Signal Tap II，添加时钟和待测试信号，预综合过滤器配置，保存生成.stp文件，合成项目并生成.bit文件，最后将位文件导出到FPGA，通过JTAG连接Signal Tap II分析器，触发测试并编程FPGA开始测试。

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working environment:

Linux

Steps

Open RTL project:
open quartus under Linux:
quartus
open project file (file that ends with .qpt)
Signal tap II
Tool -> singal Tap II
Adding clock
signal configuration -> name:clock -> filter: Signal Tap II Pre-synthesis -> list
Adding signal that you want to test
double click in the window, adding signals and hit ok
filter: pre synthesis
Hit save, xxx.stp file will be generated
Synthesizing the project, generating bit file “.sof”
export your bit file to FPGA
open signal Tap II analyzer
Hit “hardware” to connect to your JTAG
Prob the posdege of the signal that you want to trigger the test
Programming your bit file on Altera FPGA and start testing(mine FPGA is from Altera Arria V)