hdl四位二进制计数器_Verilog HDL 4位计数器问题

Modelsim6.2b编译没有问题，但是在仿真的时候输出的counter_out1的值始终是"x",那位大虾能帮我看看是什么问题？modulecounter_4_bit(clk,counter_out);inputclk;output[3:0]counter_o...

Modelsim 6.2b编译没有问题，但是在仿真的时候输出的counter_out1的值始终是"x",那位大虾能帮我看看是什么问题？

module counter_4_bit(clk, counter_out);

input clk;

output[3:0] counter_out;

reg [3:0] counter_out;

always @(posedge clk)

begin

if(counter_out == 4'b1111)

counter_out = 4'b0000;

else

counter_out = counter_out + 4'b0001;

end

endmodule

module test_for_counter;

reg clk1;

wire [3:0] counter_out1 ;

counter_4_bit counter(clk1, counter_out1);

initial

begin

clk1 = 0;

#10 clk1 = 1;

#10 clk1 = 0;

#10 clk1 = 1;

#10 clk1 = 0;

#10 clk1 = 1;

#10 clk1 = 0;

#10 clk1 = 1;

#10 clk1 = 0;

#10 clk1 = 1;

#10 $finish;

end

initial

$monitor($time, " clk1=%d, counter_out1=%d", clk1, counter_out1);

endmodule

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