低电压抖动脉冲生成Verilog代码

//Module to generate timing pulses

//DJS 6_21_16

 

`timescale 1ps / 1ps

module pulse_generator

(

clk,

sync,

ddr,

cnv_en,

cnvclk_gate,

sck_gate,

rx_start_p,

rx_start_n,

data_latch

);

 

input clk,sync,ddr;

output cnv_en,cnvclk_gate,sck_gate,rx_start_p,rx_start_n,data_latch;

 

reg cnv_en,sck_gate,rx_start_p,rx_start_n,data_latch,cnvclk_gate;

reg [8:0] count; // master counter

//this register resets to '0' while the 'sync' pulse from the PLL is 'high'.

//the following pulses are timed by this count: 'cnv_en', 'sck_gate', 'rx_reset', 'data_latch', 'cnvclk_gate'

 

reg [8:0] tsckgateh,sck_gate_length;

reg [8:0] tcnvclkgateh,cnvclk_gate_length;

reg [8:0] trxstartp,trxstartn,rx_start_length;

reg [8:0] tcnvenh,cnv_en_length;

reg [8:0] tdatalatchh;

wire ddr,sync;

 

//The first rising edge of 'clk' after the 'sync' pulse falls starts the counting process

always @ (posedge clk)

begin

trxstartp = trxstartn - 9'd2; // Time for 'rx_start_p' to go high

trxstartn = tsckgateh + 9'd3; // Time for 'rx_start_n' to go high

tsckgateh = 9'd1; // Time for 'sck_gate' to go high        

// Yields first 'SCK' edge 20nsec after 'CNV' falls

sck_gate_length = 9'd32;

tcnvenh = 9'd34; // Time for 'cnv_en' to go high

cnv_en_length = 9'd7; // Yields 'CNV' pulsewidth of 35nsec

tdatalatchh = tsckgateh + sck_gate_length + 9'd4; // Time for 'data_latch' to go high

tcnvclkgateh = tsckgateh;

cnvclk_gate_length = 9'd16;

if(ddr)

rx_start_length = 9'd4;

else

rx_start_length = 9'd2;     

end

 

initial

  count = 0;

 

always @ (posedge clk)

    if (sync)

  count <= 7'd0;

 else

  count <= count + 7'd1;

 

//generate the 'cnv_en' pulse

always @ (posedge clk)

if (count == tcnvenh)

cnv_en <= 1'b1;

else if (count == tcnvenh + cnv_en_length)

cnv_en <= 1'b0;

else

cnv_en <= cnv_en;

 

//generate the 'sck_gate' pulse

always @ (posedge clk)

if (count == tsckgateh)

sck_gate <= 1'b1;

else if (count == tsckgateh + sck_gate_length)

sck_gate <= 1'b0;

else

sck_gate <= sck_gate;

//generate the 'rx_start_p' pulse

always @ (negedge clk)

if (count == trxstartp)

rx_start_p <= 1'b1;

else if (count == trxstartp + rx_start_length)

rx_start_p <= 1'b0;

//generate the 'rxstart_n' pulse

always @ (posedge clk)

if (count == trxstartn)

rx_start_n <= 1'b1;

else if (count == trxstartn + rx_start_length)

rx_start_n <= 1'b0;

//generate the 'data_latch' pulse

always @ (posedge clk)

if (count == tdatalatchh)

data_latch <= 1'b1;

else if (count == tdatalatchh + 9'd2)

data_latch <= 1'b0;

else

data_latch <= data_latch;

//generate the 'cnvclk_gate' pulse

always @ (negedge clk)

if (count == tcnvclkgateh)

cnvclk_gate <= 1'b1;

else if (count == tcnvclkgateh + cnvclk_gate_length)

cnvclk_gate <= 1'b0;

else

cnvclk_gate <= cnvclk_gate;

 

endmodule