Synthesis
[Synth 8-5413] Mix of synchronous and asynchronous control for register p_d6_reg in module freeze_check. ["D:/uart_pro/Uart_prj.src/freeze_check.v":83]
[Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'MON_FPGA_core_0/light_control_top_0/light_driver_0/light_pwm_d2_reg[14]/Q' ["D:/uart_pro/Uart_prj.src/light_driver.v":481]
[Synth 8-6858] multi-driven net Q is connected to at least one constant driver which has been preserved, other driver is ignored ["D:/uart_pro/Uart_prj.src/light_driver.v":481]
Implementation
Write Bitstream
DRC
Pin Planning
[DRC NSTD-1] Unspecified I/O Standard: 126 out of 130 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: b_io_in[7:0], b_mon_out[7:0], g_io_in[7:0], g_mon_out[7:0], led1_out[5:0], led2_out[5:0], led3_out[2:0], led4_out[5:0], led5_out[5:0], led6_out[2:0], led_en_out[5:0], r_io_in[7:0], r_mon_out[7:0], ad1_cs_out, ad1_miso_in... and (the first 15 of 55 listed).
[DRC UCIO-1] Unconstrained Logical Port: 126 out of 130 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: b_io_in[7:0], b_mon_out[7:0], g_io_in[7:0], g_mon_out[7:0], led1_out[5:0], led2_out[5:0], led3_out[2:0], led4_out[5:0], led5_out[5:0], led6_out[2:0], led_en_out[5:0], r_io_in[7:0], r_mon_out[7:0], ad1_cs_out, ad1_miso_in... and (the first 15 of 55 listed).
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
中文解释
博客链接指向https://zipcpu.com/blog/2018/07/06/afifo.html ，标签显示与FPGA开发有关，推测内容围绕FPGA开发展开，但具体信息需点击链接查看。
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