黑金开发板状态机实现的可用按键控制的流水灯

最新推荐文章于 2023-06-20 22:01:06 发布

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最新推荐文章于 2023-06-20 22:01:06 发布

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原文链接：http://www.cnblogs.com/luxiaolai/archive/2012/07/10/2585256.html

本文介绍了一个使用Verilog实现的状态机设计实例，包括状态转移逻辑、定时控制及LED输出状态更新等内容。通过该实例，读者可以了解如何利用Verilog进行基本的状态机编程。

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module state(CLOCK,RESET,LED,KEY_UP);
input CLOCK,RESET,KEY_UP;
output reg [3:0] LED;
parameter s1=2'b00,s2=2'b01,s3=2'b10,s4=2'b11;
reg [1:0] current_state,next_state;
reg t;
parameter T1s=23'd2_000_00000;
reg [22:0] cnt;
always @ (posedge CLOCK or negedge RESET)
if(!RESET)
  begin
  cnt<=0;
  t<=0;
  end
    else if(cnt==T1s)
      begin
      cnt<=0;
      t<=~t;
      end
       else
        cnt<=cnt+1;
//assign t=(cnt==T1s)? 1'b1:1'b0;

always @ (posedge t or negedge RESET)
if(!RESET)
current_state<=s1;
  else
   current_state<=next_state;

always @ (current_state)
begin
next_state=s1;
case(current_state)
  s1: if(KEY_UP) next_state=s2;else next_state=s4;
  s2: if(KEY_UP) next_state=s3;else next_state=s1;
  s3: if(KEY_UP) next_state=s4;else next_state=s2;
  s4: if(KEY_UP) next_state=s1;else next_state=s3;
  default: next_state=s1;
  endcase
end

always @ (posedge t or negedge RESET)
if(!RESET)
LED<=4'b0000;
else
case(next_state)
  s1: LED<=4'b0001;
  s2: LED<=4'b0010;
  s3: LED<=4'b0100;
  s4: LED<=4'b1000;
  default: LED<=4'bzzzz;
endcase
endmodule

转载于:https://www.cnblogs.com/luxiaolai/archive/2012/07/10/2585256.html