clock uncertainty

clock uncertainty http://shunlang.blogbus.com/logs/71012206.html 发现以前的理解有些错误，更正一下 Pre CTS：Clock Uncertainty = Clock skew + Clock jitter + Margin Post CTS：Clock Uncertainty = Clock jitter + Margin Jitter is a quantitative measure for the clock uncertainty ，it's a really clock ,output of pll.osc Clock latency is defined as the amount of time from the clock origin point to the sync pin of the flop and uncertainity is jitter which is generated by the oscillator that is PLL Clock Skew is the difference between the clock arrival times at two different nodes (a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew. (b) The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter. (c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew. 在post CTS时，时序一定要记得设置set_propagated_clock，它包含了布局布线后真实的时钟信息。 还需要设置set_clock_latency -source 和PLL产生的 set_clock_uncertainty 这两个都是综合模块的外部环境造成的影响。 set_clock_uncertainty 主要是考虑实现是工艺偏差情况下，所做设计依然是可以工作的，既设计具有较强的鲁棒性。

转载于:https://www.cnblogs.com/asic/archive/2011/09/02/2163290.html