mine:about CP15

结合MMU相关信息，一起看！

CP15中相关寄存器介绍于设置： 

REGISTER 0: ID CODE REGISTER
This is a read-only register which returns a 32-bit device ID code.
The ID code register is accessed by reading CP15 register 0 with the opcode_2 field set to any value other than 1
(the CRm field should be zero when reading). For example:
MRC p15,0,Rd,c0,c0,0; returns ID register

 

 

REGISTER 0: CACHE TYPE REGISTER
This is a read-only register which contains information about the size and architecture of the caches, allowing
operating systems to establish how to perform such operations as cache cleaning and lockdown. Future ARM
cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their
operating systems.The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1. For example:
MRC p15,0,Rd,c0,c0,1; returns cache details

 

 

REGISTER 1: CONTROL REGISTER//vital
This register contains the control bits of the ARM920T. All reserved bits should either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. To read and
write this register:
MRC p15, 0, Rd, c1, c0, 0; read control register
MCR p15, 0, Rd, c1, c0, 0; write control register

 

31 iA bit      Asynchronous clock select See Table 2-11 on page 2-11.
30 nF bit      notFastBus select See Table 2-11 on page 2-11.
29:15          – Reserved Read = Unpredictable
                                   Write = Should be zero
14 RR bit     Round robin replacement 0 = Random replacement
                                                  1 = Round robin replacement
13 V bit       Base location of exception registers
                          0 = Low addresses = 0x0000 0000
                          1 = High addresses = 0xFFFF 0000
12 I bit        Instruction cache enable 0 = Instruction cache disabled
                                                     1 = Instruction cache enabled
11:10          – Reserved Read = 00
                                  Write = 00
9 R bit          ROM protection This bit modifies the MMU protection system.
                   See Table 3-6 on page 3-20
8 S bit          System protection This bit modifies the MMU protection system.
                    See Table 3-6 on page 3-20
7 B bit               Big-endian/little-endian 0 = Little-endian operation
                                                          1 = Big-endian operation
6:3                – Reserved Read = 1111
                                    Write = 1111
2 C bit            Data cache enable 0 = Data cache disabled
                                                1 = Data cache enabled
1 A bit            Alignment fault enable Data address alignment fault checing.
                                              0 = Fault checking disabled
                                              1 = Fault checking enabled
0 M bit             MMU enable 0 = MMU disabled

 

 

Clocking Mode                 iA                    nF
FastBus mode                  0                      0
Reserved                         1                      0
Synchronous                    0                       1
Asynchronous                  1                        1

 

 

REGISTER 2: TRANSLATION TABLE BASE (TTB) REGISTER
This is the translation table base register, for the currently active first level translation table。(it hold the the physical address of the base of transaltion table! )

 

The following instructions can be used to access the TTB:
MRC p15, 0, Rd, c2, c0, 0; read TTB register
MCR p15, 0, Rd, c2, c0, 0; write TTB register

 

REGISTER 3: DOMAIN ACCESS CONTROL REGISTER
Register 3 is the read/write domain access control register consisting of sixteen 2-bit fields. Each of these 2-bit fields defines the access permissions for the domains

The encoding of the two bit domain access permission field is given below :

Value      Meaning           Notes
00           No Access       Any access will generate a domain fault.
01          Client              Accesses are checked against access permission  bit in the section or page descriptor.
10            Reserved        Reserved.

11            Manager         Accesses are not checked against the accese permission bits so a permission fault cannot be generated

 

MRC p15, 0, Rd, c3, c0, 0; read domain 15:0 access permissions
MCR p15, 0, Rd, c3, c0, 0; write domain 15:0 access permissions

REGISTER 4: RESERVED

REGISTER 5: FAULT STATUS REGISTERS
Register 5 is the fault status register (FSR). The FSR contains the source of the last data fault, indicating the domain and type of access being attempted when the data abort occurred.

The following instructions can be used to access the data and prefetch FSR:
MRC p15, 0, Rd, c5, c0, 0 ;read data FSR value
MCR p15, 0, Rd, c5, c0, 0 ;write data FSR value
MRC p15, 0, Rd, c5, c0, 1 ;read prefetch FSR value
MCR p15, 0, Rd, c5, c0, 1 ;write prefetch FSR value
The ability to write to the FSR is useful for a debugger to restore the value of the FSR. The register should be written
using the read-modify-write method. Bits[31:8] should be zero.

 

REGISTER 6: FAULT ADDRESS REGISTER
Register 6 is the fault address register (FAR) which contains the modified virtual address of the access being attempted when the last fault occurred. The FAR is only updated for data faults, not for prefetch faults.
(The address for a prefetch fault can be found in R14.)
The following instructions can be used to access the FAR:
MRC p15, 0, Rd, c6, c0, 0 ;read FAR data
MCR p15, 0, Rd, c6, c0, 0 ;write FAR data
The ability to write to the FAR is intended for a debugger to restore a previous state.

 

 

REGISTER 7: CACHE OPERATIONS //vital
Register 7 is a write-only register used to manage the instruction and data caches, ICache and DCache.
The cache operations provided by register 7 are described below:

 

Function                                                                  Instruction
Invalidate ICache                                                     MCR p15,0,Rd,c7,c7,0
Invalidate ICache                                                     MCR p15,0,Rd,c7,c5,0
Invalidate ICache single entry (using MVA)                  MCR p15,0,Rd,c7,c5,1
Prefetch ICache line (using MVA)                                 MCR p15,0,Rd,c7,c13,1
Invalidate DCache                                                    MCR p15,0,Rd,c7,c6,0
Invalidate DCache single entry (using MVA)                   MCR p15,0,Rd,c7,c6,1
Clean DCache single entry (using MVA)                       MCR p15,0,Rd,c7,c10,1
Clean and Invalidate DCache entry                             MCR p15,0,Rd,c7,c14,1
Clean DCache single entry                                         MCR p15,0,Rd,c7,c10,2
Clean and Invalidate DCache entry (using index)           MCR p15,0,Rd,c7,c14,2
Drain write buffer (1)                                                MCR p15,0,Rd,c7,c10,4
Wait for interrupt (2)                                                MCR p15,0,Rd,c7,c0,4

 

REGISTER 8: TLB OPERATIONS
Register 8 is a write-only register used to manage the translation lookaside buffers (TLBs), the instruction TLB and the data TLB.
Five TLB operations are defined and the function to be performed is selected by the opcode_2 and CRm fields in the
MCR instruction used to write CP15 register 8. Writing other opcode_2 or CRm values is unpredictable. Reading from
CP15 register 8 is unpredictable.
the next shows instructions that can be used to perform TLB operations using register 8.

Function Data                                                           Instruction
Invalidate TLB(s)                                                        MCR p15,0,Rd,c8,c7,0
Invalidate I TLB                                                          MCR p15,0,Rd,c8,c5,0
Invalidate I TLB single entry (using MVA)                       MCR p15,0,Rd,c8,c5,1
Invalidate D TLB                                                         MCR p15,0,Rd,c8,c6,0
Invalidate D TLB single entry (using MVA)                      MCR p15,0,Rd,c8,c6,1

NOTE: These functions invalidate all the un-preserved entries in the TLB.
Invalidate TLB single entry functions invalidate any TLB entry corresponding to the modified virtual address given in
Rd, regardless of its preserved state.

//i can't understand the REGISTER 9/10 clealy!!!!!!!!

update:

Lock：将某个地址的数据锁定在Cache中，确保不被替换掉。在实时系统中，这样做可以保证某个地址的数据能在一个确定的时间内访问到。

REGISTER 9: CACHE LOCK DOWN REGISTER
Register 9 is the cache lock down register. The cache lock down register is 0x0 on reset. The cache lock down
register allows software to control which cache line in the ICache or DCache respectively is loaded for a linefill and to
prevent lines in the ICache or DCache from being evicted during a linefill, locking them into the cache.
There is a register for each of the ICache and DCache, the value of opcode_2 determines which cache register to
access:
opcode_2 = 0x0 causes the DCache register to be accessed
opcode_2 = 0x1 causes the ICache register to be accessed.
The Opcode_1 and CRm fields should be zero.
Reading CP15 register 9 returns the value of the cache lock down register, which is the base pointer for all cache
segments.

 

REGISTER 10: TLB LOCK DOWN REGISTER
Register 10 is the TLB lock down register. The TLB lock down register is 0x0 on reset. There is a TLB lock down
register for each of the TLBs, the value of opcode_2 determines which TLB register to access:
opcode_2 = 0x0 causes the D TLB register to be accessed
opcode_2 = 0x1 causes the I TLB register to be accessed.
Reading CP15 register 10 returns the value of the TLB lock down counter base register, the current victim number
and the preserve bit (P bit). Note that bits [19:1] are unpredictable when read.
Writing CP15 register 10 updates the TLB lock down counter base register, the current victim pointer and the state of
the preserve bit. Bits [19:1] should be zero when written.

 

 

REGISTER 13: PROCESS ID
Register 13 is the process identifier register. The process identifier register is 0x0 on reset.
Reading from CP15 register 13 returns the value of the process identifier. Writing CP15 register 13 updates the
process identifier to the value in bits [31:25]. Bits [24:0] should be zero.

 

Register 13 can be accessed using the following instructions:
MRC p15, 0, Rd, c13, c0, 0 ;read process identifier
MCR p15, 0, Rd, c13, c0, 0 ;write process identifier

 

REGISTER 15: TEST CONFIGURATION REGISTER
Register 15 is used for test purposes. Accessing (reading or writing) this register will cause the ARM920T to have
unpredictable behavior.