记录MMU

最新推荐文章于 2025-04-22 11:42:19 发布

vincent_zou

最新推荐文章于 2025-04-22 11:42:19 发布

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分类专栏： arm硬件相关文章标签： permissions access translation algorithm scheme features

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本文详细介绍了ARMv4内存管理单元(MMU)的主要特性，包括标准的映射大小、域和访问保护方案；支持1MB、64KB、4KB和新的1KB页面大小；每个页面的访问权限可以单独指定；硬件实现16个域；64项指令TLB和64项数据TLB；硬件页表遍历；循环替换算法；通过CP15寄存器8整体或部分无效TLB。

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The MMU features are:
· standard ARM V4 MMU mapping sizes, domains, and access protection scheme
· mapping sizes are 1MB sections, 64KB large pages, 4KB small pages and new 1KB tiny pages
· access permissions for sections
· access permissions for large pages and small pages can be specified separately for each quarter of the page
(these quarters are called sub-pages)
· 16 domains（D0 ~ D15） implemented in hardware
· 64 entry instruction TLB (Each TLB caches 64 translated entries)and 64 entry data TLB
· hardware page table walks
· round-robin replacement algorithm (also called cyclic)
· invalidate whole TLB via CP15 Register 8
· invalidate TLB entry, selected by modified virtual address, via CP15 register 8
· independent lockdown of instruction TLB and data TLB via CP15 register 10.

The MMU translates virtual addresses generated by the CPU core (and by CP15 register 13) into physical addresses
to access external memory. It also derives and checks the access permission, using a translation lookaside buffer
(TLB).