519_900

本文介绍了一种名为“非常平滑分解”的算法实现,通过枚举和数据挖掘的方法解决特定数学问题。该算法利用BigInteger进行大数运算,针对输入字符串进行数值转换,并计算该数值在特定条件下能被2到16之间的数整除的最大次数。进而通过动态规划方法找出所有可能的分解方案数量。

1. 数据小, 充分挖潜数据的特点

2. 该DP的DP, 该枚举的枚举

3. 注意将一些枚举简化成O(1)的式子:

    a[i] + a[i + 1] + ... + a[j] = sum[j] - sum[i - 1]

 

import java.util.*;
import java.util.regex.*;
import java.text.*;
import java.math.*;
import java.awt.geom.*;

public class VerySmoothDecompositions
{
	public BigInteger [] BI = new BigInteger[16];
	public int [] cnt = new int[16];
	public int mod = 1000000009;
	
	public void cal_BI() {
		for (int i = 0; i < 16; ++i) {
			BI[i] = BigInteger.valueOf(i);
			cnt[i] = 0;
		}
	}
	public int solve(String[] dig)
	{
		cal_BI();
		String num = "";
		for (int i = 0 ; i < dig.length; ++i) {
			num += dig[i];
		}
		BigInteger n = BI[0];
		for (int i = 0 ; i < num.length(); ++i) {
			n = n.multiply(BI[10]);
			int k = num.charAt(i) - '0';
			n = n.add(BI[k]);
		}
		for (int i = 2; i < 16; ++i) {
			while (n.mod(BI[i]).equals(BI[0])) {
				cnt[i]++;
				n = n.divide(BI[i]);
			}
		}
		if (!n.equals(BI[1])) return 0;
		int [][] d = new int [cnt[2] + 1][cnt[3] + 1];
		//2, 4, 8, 16, 3, 9, 6, 12
		int [] dx = {1, 2, 3, 4, 0, 0, 1, 2};
		int [] dy = {0, 0, 0, 0, 1, 2, 1, 1};
		
		d[0][0] = 1;
		for (int i = 0; i < dx.length; ++i) {
			for (int j = dx[i]; j <= cnt[2]; ++j) {
				for (int k = dy[i]; k <= cnt[3]; ++k) {
					d[j][k] += d[j - dx[i]][k - dy[i]];
					if (d[j][k] >= mod) d[j][k] -= mod;
				}
			}
		}
		for (int i = 0; i <= cnt[2]; ++i) {
			for (int j = 1; j <= cnt[3]; ++j) {
				d[i][j] += d[i][j - 1];
				if (d[i][j] >= mod) d[i][j] -= mod;
			}
		}
		int ans = 0;
		for (int i = 0; i <= cnt[7]; ++i) {
			for (int j = 0; j <= cnt[5]; ++j) {
				int c2 = cnt[2] - i - j;
				if (c2 < 0) break;
				int c5 = cnt[5] - j;
				// 3
				int ok0 = cnt[3] - c5, ok1 = cnt[3];
				if (ok0 < 0) ok0 = 0;
				ans += d[c2][ok1];
				if (ans >= mod) ans -= mod;
				if (ok0 > 0) ans -= d[c2][ok0 - 1];
				if (ans < 0) ans += mod;
			}
		}
		return ans;
	}
}

 

写出下面代码用到的AT命令,讲解每个AT命令的具体的含义: #include <base/functional/bind.h> 27 #include <base/functional/callback_forward.h> 28 #include <string.h> 29 30 #include "device/include/esco_parameters.h" 31 #include "hcidefs.h" 32 #include "hcimsgs.h" 33 #include "internal_include/bt_target.h" 34 #include "main/shim/acl_api.h" 35 #include "osi/include/allocator.h" 36 #include "stack/include/bt_dev_class.h" 37 #include "stack/include/bt_hdr.h" 38 #include "stack/include/bt_lap.h" 39 #include "stack/include/bt_octets.h" 40 #include "stack/include/bt_types.h" 41 #include "stack/include/btu_hcif.h" 42 #include "types/raw_address.h" 43 44 /* Message by message.... */ 45 46 #define HCIC_PARAM_SIZE_INQUIRY 5 47 48 #define HCIC_INQ_INQ_LAP_OFF 0 49 #define HCIC_INQ_DUR_OFF 3 50 #define HCIC_INQ_RSP_CNT_OFF 4 51 52 /* Periodic Inquiry Mode */ 53 #define HCIC_PARAM_SIZE_PER_INQ_MODE 9 54 55 #define HCI_PER_INQ_MAX_INTRVL_OFF 0 56 #define HCI_PER_INQ_MIN_INTRVL_OFF 2 57 #define HCI_PER_INQ_INQ_LAP_OFF 4 58 #define HCI_PER_INQ_DURATION_OFF 7 59 #define HCI_PER_INQ_RSP_CNT_OFF 8 60 /* Periodic Inquiry Mode */ 61 62 /* Exit Periodic Inquiry Mode */ 63 #define HCIC_PARAM_SIZE_EXIT_PER_INQ 0 64 65 /* Create Connection */ 66 #define HCIC_PARAM_SIZE_CREATE_CONN 13 67 68 #define HCIC_CR_CONN_BD_ADDR_OFF 0 69 #define HCIC_CR_CONN_PKT_TYPES_OFF 6 70 #define HCIC_CR_CONN_REP_MODE_OFF 8 71 #define HCIC_CR_CONN_PAGE_SCAN_MODE_OFF 9 72 #define HCIC_CR_CONN_CLK_OFF_OFF 10 73 #define HCIC_CR_CONN_ALLOW_SWITCH_OFF 12 74 /* Create Connection */ 75 76 /* Disconnect */ 77 #define HCIC_PARAM_SIZE_DISCONNECT 3 78 79 #define HCI_DISC_HANDLE_OFF 0 80 #define HCI_DISC_REASON_OFF 2 81 /* Disconnect */ 82 83 /* Add SCO Connection */ 84 #define HCIC_PARAM_SIZE_ADD_SCO_CONN 4 85 86 #define HCI_ADD_SCO_HANDLE_OFF 0 87 #define HCI_ADD_SCO_PACKET_TYPES_OFF 2 88 /* Add SCO Connection */ 89 90 /* Create Connection Cancel */ 91 #define HCIC_PARAM_SIZE_CREATE_CONN_CANCEL 6 92 93 #define HCIC_CR_CONN_CANCEL_BD_ADDR_OFF 0 94 /* Create Connection Cancel */ 95 96 /* Accept Connection Request */ 97 #define HCIC_PARAM_SIZE_ACCEPT_CONN 7 98 99 #define HCI_ACC_CONN_BD_ADDR_OFF 0 100 #define HCI_ACC_CONN_ROLE_OFF 6 101 /* Accept Connection Request */ 102 103 /* Reject Connection Request */ 104 #define HCIC_PARAM_SIZE_REJECT_CONN 7 105 106 #define HCI_REJ_CONN_BD_ADDR_OFF 0 107 #define HCI_REJ_CONN_REASON_OFF 6 108 /* Reject Connection Request */ 109 110 /* Link Key Request Reply */ 111 #define HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY 22 112 113 #define HCI_LINK_KEY_REPLY_BD_ADDR_OFF 0 114 #define HCI_LINK_KEY_REPLY_LINK_KEY_OFF 6 115 /* Link Key Request Reply */ 116 117 /* Link Key Request Neg Reply */ 118 #define HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY 6 119 120 #define HCI_LINK_KEY_NEG_REP_BD_ADR_OFF 0 121 /* Link Key Request Neg Reply */ 122 123 /* PIN Code Request Reply */ 124 #define HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY 23 125 126 #define HCI_PIN_CODE_REPLY_BD_ADDR_OFF 0 127 #define HCI_PIN_CODE_REPLY_PIN_LEN_OFF 6 128 #define HCI_PIN_CODE_REPLY_PIN_CODE_OFF 7 129 /* PIN Code Request Reply */ 130 131 /* Link Key Request Neg Reply */ 132 #define HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY 6 133 134 #define HCI_PIN_CODE_NEG_REP_BD_ADR_OFF 0 135 /* Link Key Request Neg Reply */ 136 137 /* Change Connection Type */ 138 #define HCIC_PARAM_SIZE_CHANGE_CONN_TYPE 4 139 140 #define HCI_CHNG_PKT_TYPE_HANDLE_OFF 0 141 #define HCI_CHNG_PKT_TYPE_PKT_TYPE_OFF 2 142 /* Change Connection Type */ 143 144 #define HCIC_PARAM_SIZE_CMD_HANDLE 2 145 146 #define HCI_CMD_HANDLE_HANDLE_OFF 0 147 148 /* Set Connection Encryption */ 149 #define HCIC_PARAM_SIZE_SET_CONN_ENCRYPT 3 150 151 #define HCI_SET_ENCRYPT_HANDLE_OFF 0 152 #define HCI_SET_ENCRYPT_ENABLE_OFF 2 153 /* Set Connection Encryption */ 154 155 /* Remote Name Request */ 156 #define HCIC_PARAM_SIZE_RMT_NAME_REQ 10 157 158 #define HCI_RMT_NAME_BD_ADDR_OFF 0 159 #define HCI_RMT_NAME_REP_MODE_OFF 6 160 #define HCI_RMT_NAME_PAGE_SCAN_MODE_OFF 7 161 #define HCI_RMT_NAME_CLK_OFF_OFF 8 162 /* Remote Name Request */ 163 164 /* Remote Name Request Cancel */ 165 #define HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL 6 166 167 #define HCI_RMT_NAME_CANCEL_BD_ADDR_OFF 0 168 /* Remote Name Request Cancel */ 169 170 /* Remote Extended Features */ 171 #define HCIC_PARAM_SIZE_RMT_EXT_FEATURES 3 172 173 #define HCI_RMT_EXT_FEATURES_HANDLE_OFF 0 174 #define HCI_RMT_EXT_FEATURES_PAGE_NUM_OFF 2 175 /* Remote Extended Features */ 176 177 #define HCIC_PARAM_SIZE_SETUP_ESCO 17 178 179 #define HCI_SETUP_ESCO_HANDLE_OFF 0 180 #define HCI_SETUP_ESCO_TX_BW_OFF 2 181 #define HCI_SETUP_ESCO_RX_BW_OFF 6 182 #define HCI_SETUP_ESCO_MAX_LAT_OFF 10 183 #define HCI_SETUP_ESCO_VOICE_OFF 12 184 #define HCI_SETUP_ESCO_RETRAN_EFF_OFF 14 185 #define HCI_SETUP_ESCO_PKT_TYPES_OFF 15 186 187 #define HCIC_PARAM_SIZE_ACCEPT_ESCO 21 188 189 #define HCI_ACCEPT_ESCO_BDADDR_OFF 0 190 #define HCI_ACCEPT_ESCO_TX_BW_OFF 6 191 #define HCI_ACCEPT_ESCO_RX_BW_OFF 10 192 #define HCI_ACCEPT_ESCO_MAX_LAT_OFF 14 193 #define HCI_ACCEPT_ESCO_VOICE_OFF 16 194 #define HCI_ACCEPT_ESCO_RETRAN_EFF_OFF 18 195 #define HCI_ACCEPT_ESCO_PKT_TYPES_OFF 19 196 197 #define HCIC_PARAM_SIZE_REJECT_ESCO 7 198 199 #define HCI_REJECT_ESCO_BDADDR_OFF 0 200 #define HCI_REJECT_ESCO_REASON_OFF 6 201 202 /* Hold Mode */ 203 #define HCIC_PARAM_SIZE_HOLD_MODE 6 204 205 #define HCI_HOLD_MODE_HANDLE_OFF 0 206 #define HCI_HOLD_MODE_MAX_PER_OFF 2 207 #define HCI_HOLD_MODE_MIN_PER_OFF 4 208 /* Hold Mode */ 209 210 /* Sniff Mode */ 211 #define HCIC_PARAM_SIZE_SNIFF_MODE 10 212 213 #define HCI_SNIFF_MODE_HANDLE_OFF 0 214 #define HCI_SNIFF_MODE_MAX_PER_OFF 2 215 #define HCI_SNIFF_MODE_MIN_PER_OFF 4 216 #define HCI_SNIFF_MODE_ATTEMPT_OFF 6 217 #define HCI_SNIFF_MODE_TIMEOUT_OFF 8 218 /* Sniff Mode */ 219 220 /* Park Mode */ 221 #define HCIC_PARAM_SIZE_PARK_MODE 6 222 223 #define HCI_PARK_MODE_HANDLE_OFF 0 224 #define HCI_PARK_MODE_MAX_PER_OFF 2 225 #define HCI_PARK_MODE_MIN_PER_OFF 4 226 /* Park Mode */ 227 228 /* QoS Setup */ 229 #define HCIC_PARAM_SIZE_QOS_SETUP 20 230 231 #define HCI_QOS_HANDLE_OFF 0 232 #define HCI_QOS_FLAGS_OFF 2 233 #define HCI_QOS_SERVICE_TYPE_OFF 3 234 #define HCI_QOS_TOKEN_RATE_OFF 4 235 #define HCI_QOS_PEAK_BANDWIDTH_OFF 8 236 #define HCI_QOS_LATENCY_OFF 12 237 #define HCI_QOS_DELAY_VAR_OFF 16 238 /* QoS Setup */ 239 240 #define HCIC_PARAM_SIZE_SWITCH_ROLE 7 241 242 #define HCI_SWITCH_BD_ADDR_OFF 0 243 #define HCI_SWITCH_ROLE_OFF 6 244 /* Switch Role Request */ 245 246 /* Write Policy Settings */ 247 #define HCIC_PARAM_SIZE_WRITE_POLICY_SET 4 248 249 #define HCI_WRITE_POLICY_HANDLE_OFF 0 250 #define HCI_WRITE_POLICY_SETTINGS_OFF 2 251 /* Write Policy Settings */ 252 253 /* Write Default Policy Settings */ 254 #define HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET 2 255 256 #define HCI_WRITE_DEF_POLICY_SETTINGS_OFF 0 257 /* Write Default Policy Settings */ 258 259 #define HCIC_PARAM_SIZE_SNIFF_SUB_RATE 8 260 261 #define HCI_SNIFF_SUB_RATE_HANDLE_OFF 0 262 #define HCI_SNIFF_SUB_RATE_MAX_LAT_OFF 2 263 #define HCI_SNIFF_SUB_RATE_MIN_REM_LAT_OFF 4 264 #define HCI_SNIFF_SUB_RATE_MIN_LOC_LAT_OFF 6 265 /* Sniff Subrating */ 266 267 /* Extended Inquiry Response */ 268 #define HCIC_PARAM_SIZE_EXT_INQ_RESP 241 269 270 #define HCIC_EXT_INQ_RESP_FEC_OFF 0 271 #define HCIC_EXT_INQ_RESP_RESPONSE 1 272 /* IO Capabilities Response */ 273 #define HCIC_PARAM_SIZE_IO_CAP_RESP 9 274 275 #define HCI_IO_CAP_BD_ADDR_OFF 0 276 #define HCI_IO_CAPABILITY_OFF 6 277 #define HCI_IO_CAP_OOB_DATA_OFF 7 278 #define HCI_IO_CAP_AUTH_REQ_OFF 8 279 280 /* IO Capabilities Req Neg Reply */ 281 #define HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY 7 282 283 #define HCI_IO_CAP_NR_BD_ADDR_OFF 0 284 #define HCI_IO_CAP_NR_ERR_CODE 6 285 286 /* Read Local OOB Data */ 287 #define HCIC_PARAM_SIZE_R_LOCAL_OOB 0 288 289 /* Read Local OOB Extended Data */ 290 #define HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED 0 291 292 #define HCIC_PARAM_SIZE_UCONF_REPLY 6 293 294 #define HCI_USER_CONF_BD_ADDR_OFF 0 295 296 #define HCIC_PARAM_SIZE_U_PKEY_REPLY 10 297 298 #define HCI_USER_PASSKEY_BD_ADDR_OFF 0 299 #define HCI_USER_PASSKEY_VALUE_OFF 6 300 301 #define HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY 6 302 303 #define HCI_USER_PASSKEY_NEG_BD_ADDR_OFF 0 304 305 /* Remote OOB Data Request Reply */ 306 #define HCIC_PARAM_SIZE_REM_OOB_REPLY 38 307 308 #define HCI_REM_OOB_DATA_BD_ADDR_OFF 0 309 #define HCI_REM_OOB_DATA_C_OFF 6 310 #define HCI_REM_OOB_DATA_R_OFF 22 311 312 /* Remote OOB Data Request Negative Reply */ 313 #define HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY 6 314 315 #define HCI_REM_OOB_DATA_NEG_BD_ADDR_OFF 0 316 317 /* Read Tx Power Level */ 318 #define HCIC_PARAM_SIZE_R_TX_POWER 0 319 320 /* Read Default Erroneous Data Reporting */ 321 #define HCIC_PARAM_SIZE_R_ERR_DATA_RPT 0 322 323 #define HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF 7 324 325 #define HCI_SEND_KEYPRESS_NOTIF_BD_ADDR_OFF 0 326 #define HCI_SEND_KEYPRESS_NOTIF_NOTIF_OFF 6 327 328 /**** end of Simple Pairing Commands ****/ 329 330 #define HCIC_PARAM_SIZE_SET_EVT_FILTER 9 331 332 #define HCI_FILT_COND_FILT_TYPE_OFF 0 333 #define HCI_FILT_COND_COND_TYPE_OFF 1 334 #define HCI_FILT_COND_FILT_OFF 2 335 /* Set Event Filter */ 336 337 /* Delete Stored Key */ 338 #define HCIC_PARAM_SIZE_DELETE_STORED_KEY 7 339 340 #define HCI_DELETE_KEY_BD_ADDR_OFF 0 341 #define HCI_DELETE_KEY_ALL_FLAG_OFF 6 342 /* Delete Stored Key */ 343 344 /* Change Local Name */ 345 #define HCIC_PARAM_SIZE_CHANGE_NAME BD_NAME_LEN 346 347 #define HCI_CHANGE_NAME_NAME_OFF 0 348 /* Change Local Name */ 349 350 #define HCIC_PARAM_SIZE_READ_CMD 0 351 352 #define HCIC_PARAM_SIZE_WRITE_PARAM1 1 353 354 #define HCIC_WRITE_PARAM1_PARAM_OFF 0 355 356 #define HCIC_PARAM_SIZE_WRITE_PARAM2 2 357 358 #define HCIC_WRITE_PARAM2_PARAM_OFF 0 359 360 #define HCIC_PARAM_SIZE_WRITE_PARAM3 3 361 362 #define HCIC_WRITE_PARAM3_PARAM_OFF 0 363 364 #define HCIC_PARAM_SIZE_SET_AFH_CHANNELS 10 365 366 #define HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN 59 367 #define HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN 63 368 369 #define HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG 4 370 371 #define HCI_SCAN_CFG_INTERVAL_OFF 0 372 #define HCI_SCAN_CFG_WINDOW_OFF 2 373 /* Write Page Scan Activity */ 374 375 /* Write Inquiry Scan Activity */ 376 #define HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG 4 377 378 #define HCI_SCAN_CFG_INTERVAL_OFF 0 379 #define HCI_SCAN_CFG_WINDOW_OFF 2 380 /* Write Inquiry Scan Activity */ 381 382 /* Host Controller to Host flow control */ 383 #define HCI_HOST_FLOW_CTRL_OFF 0 384 #define HCI_HOST_FLOW_CTRL_ACL_ON 1 385 #define HCI_HOST_FLOW_CTRL_SCO_ON 2 386 #define HCI_HOST_FLOW_CTRL_BOTH_ON 3 387 388 #define HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT 4 389 390 #define HCI_FLUSH_TOUT_HANDLE_OFF 0 391 #define HCI_FLUSH_TOUT_TOUT_OFF 2 392 393 #define HCIC_PARAM_SIZE_READ_TX_POWER 3 394 395 #define HCI_READ_TX_POWER_HANDLE_OFF 0 396 #define HCI_READ_TX_POWER_TYPE_OFF 2 397 398 /* Read transmit power level parameter */ 399 #define HCI_READ_CURRENT 0x00 400 #define HCI_READ_MAXIMUM 0x01 401 402 #define HCIC_PARAM_SIZE_NUM_PKTS_DONE_SIZE sizeof(btmsg_hcic_num_pkts_done_t) 403 404 #define MAX_DATA_HANDLES 10 405 406 #define HCI_PKTS_DONE_NUM_HANDLES_OFF 0 407 #define HCI_PKTS_DONE_HANDLE_OFF 1 408 #define HCI_PKTS_DONE_NUM_PKTS_OFF 3 409 410 #define HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT 4 411 412 #define HCI_LINK_SUPER_TOUT_HANDLE_OFF 0 413 #define HCI_LINK_SUPER_TOUT_TOUT_OFF 2 414 /* Write Link Supervision Timeout */ 415 416 #define MAX_IAC_LAPS 0x40 417 418 #define HCI_WRITE_IAC_LAP_NUM_OFF 0 419 #define HCI_WRITE_IAC_LAP_LAP_OFF 1 420 /* Write Current IAC LAP */ 421 422 #define HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH 3 423 424 /******************************************************************************* 425 * BLE Commands 426 * Note: "local_controller_id" is for transport, not counted in HCI 427 * message size 428 ******************************************************************************/ 429 #define HCIC_BLE_RAND_DI_SIZE 8 430 #define HCIC_BLE_IRK_SIZE 16 431 432 #define HCIC_PARAM_SIZE_SET_USED_FEAT_CMD 8 433 #define HCIC_PARAM_SIZE_WRITE_RANDOM_ADDR_CMD 6 434 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_PARAMS 15 435 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_RSP 31 436 #define HCIC_PARAM_SIZE_WRITE_ADV_ENABLE 1 437 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_PARAM 7 438 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_ENABLE 2 439 #define HCIC_PARAM_SIZE_BLE_CREATE_LL_CONN 25 440 #define HCIC_PARAM_SIZE_BLE_CREATE_CONN_CANCEL 0 441 #define HCIC_PARAM_SIZE_CLEAR_ACCEPTLIST 0 442 #define HCIC_PARAM_SIZE_ADD_ACCEPTLIST 7 443 #define HCIC_PARAM_SIZE_REMOVE_ACCEPTLIST 7 444 #define HCIC_PARAM_SIZE_BLE_UPD_LL_CONN_PARAMS 14 445 #define HCIC_PARAM_SIZE_SET_HOST_CHNL_CLASS 5 446 #define HCIC_PARAM_SIZE_READ_CHNL_MAP 2 447 #define HCIC_PARAM_SIZE_BLE_READ_REMOTE_FEAT 2 448 #define HCIC_PARAM_SIZE_BLE_ENCRYPT 32 449 #define HCIC_PARAM_SIZE_WRITE_LE_HOST_SUPPORTED 2 450 451 #define HCIC_BLE_RAND_DI_SIZE 8 452 #define HCIC_BLE_ENCRYPT_KEY_SIZE 16 453 #define HCIC_PARAM_SIZE_BLE_START_ENC \ 454 (4 + HCIC_BLE_RAND_DI_SIZE + HCIC_BLE_ENCRYPT_KEY_SIZE) 455 #define HCIC_PARAM_SIZE_LTK_REQ_REPLY (2 + HCIC_BLE_ENCRYPT_KEY_SIZE) 456 #define HCIC_PARAM_SIZE_LTK_REQ_NEG_REPLY 2 457 #define HCIC_BLE_CHNL_MAP_SIZE 5 458 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_DATA 31 459 460 #define HCIC_PARAM_SIZE_BLE_ADD_DEV_RESOLVING_LIST (7 + HCIC_BLE_IRK_SIZE * 2) 461 #define HCIC_PARAM_SIZE_BLE_RM_DEV_RESOLVING_LIST 7 462 #define HCIC_PARAM_SIZE_BLE_SET_PRIVACY_MODE 8 463 #define HCIC_PARAM_SIZE_BLE_CLEAR_RESOLVING_LIST 0 464 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVING_LIST_SIZE 0 465 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_PEER 7 466 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_LOCAL 7 467 #define HCIC_PARAM_SIZE_BLE_SET_ADDR_RESOLUTION_ENABLE 1 468 #define HCIC_PARAM_SIZE_BLE_SET_RAND_PRIV_ADDR_TIMOUT 2 469 470 #define HCIC_PARAM_SIZE_BLE_READ_PHY 2 471 #define HCIC_PARAM_SIZE_BLE_SET_DEFAULT_PHY 3 472 #define HCIC_PARAM_SIZE_BLE_SET_PHY 7 473 #define HCIC_PARAM_SIZE_BLE_ENH_RX_TEST 3 474 #define HCIC_PARAM_SIZE_BLE_ENH_TX_TEST 4 475 476 #define HCIC_PARAM_SIZE_BLE_SET_DATA_LENGTH 6 477 #define HCIC_PARAM_SIZE_BLE_WRITE_EXTENDED_SCAN_PARAM 11 478 479 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_REPLY 14 480 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_NEG_REPLY 3 481 482 static void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) { 483 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 484 uint8_t* pp = (uint8_t*)(p + 1); 485 486 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT; 487 p->offset = 0; 488 489 UINT16_TO_STREAM(pp, HCI_DISCONNECT); 490 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT); 491 UINT16_TO_STREAM(pp, handle); 492 UINT8_TO_STREAM(pp, reason); 493 494 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 495 } 496 497 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) { 498 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 499 uint8_t* pp = (uint8_t*)(p + 1); 500 501 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN; 502 p->offset = 0; 503 504 UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION); 505 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN); 506 507 UINT16_TO_STREAM(pp, handle); 508 UINT16_TO_STREAM(pp, packet_types); 509 510 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 511 } 512 513 void btsnd_hcic_create_conn_cancel(const RawAddress& dest) { 514 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 515 uint8_t* pp = (uint8_t*)(p + 1); 516 517 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL; 518 p->offset = 0; 519 520 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL); 521 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL); 522 523 BDADDR_TO_STREAM(pp, dest); 524 525 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 526 } 527 528 void btsnd_hcic_accept_conn(const RawAddress& dest, uint8_t role) { 529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 530 uint8_t* pp = (uint8_t*)(p + 1); 531 532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_CONN; 533 p->offset = 0; 534 535 UINT16_TO_STREAM(pp, HCI_ACCEPT_CONNECTION_REQUEST); 536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_CONN); 537 BDADDR_TO_STREAM(pp, dest); 538 UINT8_TO_STREAM(pp, role); 539 540 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 541 } 542 543 void btsnd_hcic_reject_conn(const RawAddress& dest, uint8_t reason) { 544 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 545 uint8_t* pp = (uint8_t*)(p + 1); 546 547 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN; 548 p->offset = 0; 549 550 UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST); 551 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN); 552 553 BDADDR_TO_STREAM(pp, dest); 554 UINT8_TO_STREAM(pp, reason); 555 556 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 557 } 558 559 void btsnd_hcic_link_key_req_reply(const RawAddress& bd_addr, 560 const LinkKey& link_key) { 561 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 562 uint8_t* pp = (uint8_t*)(p + 1); 563 564 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY; 565 p->offset = 0; 566 567 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY); 568 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY); 569 570 BDADDR_TO_STREAM(pp, bd_addr); 571 ARRAY16_TO_STREAM(pp, link_key.data()); 572 573 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 574 } 575 576 void btsnd_hcic_link_key_neg_reply(const RawAddress& bd_addr) { 577 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 578 uint8_t* pp = (uint8_t*)(p + 1); 579 580 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY; 581 p->offset = 0; 582 583 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY); 584 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY); 585 586 BDADDR_TO_STREAM(pp, bd_addr); 587 588 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 589 } 590 591 void btsnd_hcic_pin_code_req_reply(const RawAddress& bd_addr, 592 uint8_t pin_code_len, PIN_CODE pin_code) { 593 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 594 uint8_t* pp = (uint8_t*)(p + 1); 595 int i; 596 597 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY; 598 p->offset = 0; 599 600 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY); 601 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY); 602 603 BDADDR_TO_STREAM(pp, bd_addr); 604 UINT8_TO_STREAM(pp, pin_code_len); 605 606 for (i = 0; i < pin_code_len; i++) *pp++ = *pin_code++; 607 608 for (; i < PIN_CODE_LEN; i++) *pp++ = 0; 609 610 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 611 } 612 613 void btsnd_hcic_pin_code_neg_reply(const RawAddress& bd_addr) { 614 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 615 uint8_t* pp = (uint8_t*)(p + 1); 616 617 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY; 618 p->offset = 0; 619 620 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY); 621 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY); 622 623 BDADDR_TO_STREAM(pp, bd_addr); 624 625 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 626 } 627 628 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) { 629 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 630 uint8_t* pp = (uint8_t*)(p + 1); 631 632 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE; 633 p->offset = 0; 634 635 UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE); 636 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE); 637 638 UINT16_TO_STREAM(pp, handle); 639 UINT16_TO_STREAM(pp, packet_types); 640 641 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 642 } 643 644 void btsnd_hcic_auth_request(uint16_t handle) { 645 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 646 uint8_t* pp = (uint8_t*)(p + 1); 647 648 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 649 p->offset = 0; 650 651 UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED); 652 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 653 654 UINT16_TO_STREAM(pp, handle); 655 656 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 657 } 658 659 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) { 660 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 661 uint8_t* pp = (uint8_t*)(p + 1); 662 663 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT; 664 p->offset = 0; 665 666 UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION); 667 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT); 668 669 UINT16_TO_STREAM(pp, handle); 670 UINT8_TO_STREAM(pp, enable); 671 672 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 673 } 674 675 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) { 676 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 677 uint8_t* pp = (uint8_t*)(p + 1); 678 679 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES; 680 p->offset = 0; 681 682 UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES); 683 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES); 684 685 UINT16_TO_STREAM(pp, handle); 686 UINT8_TO_STREAM(pp, page_num); 687 688 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 689 } 690 691 void btsnd_hcic_rmt_ver_req(uint16_t handle) { 692 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 693 uint8_t* pp = (uint8_t*)(p + 1); 694 695 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 696 p->offset = 0; 697 698 UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO); 699 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 700 701 UINT16_TO_STREAM(pp, handle); 702 703 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 704 } 705 706 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) { 707 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 708 uint8_t* pp = (uint8_t*)(p + 1); 709 710 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 711 p->offset = 0; 712 713 UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET); 714 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 715 716 UINT16_TO_STREAM(pp, handle); 717 718 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 719 } 720 721 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth, 722 uint32_t receive_bandwidth, 723 uint16_t max_latency, uint16_t voice, 724 uint8_t retrans_effort, uint16_t packet_types) { 725 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 726 uint8_t* pp = (uint8_t*)(p + 1); 727 728 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO; 729 p->offset = 0; 730 731 UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION); 732 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO); 733 734 UINT16_TO_STREAM(pp, handle); 735 UINT32_TO_STREAM(pp, transmit_bandwidth); 736 UINT32_TO_STREAM(pp, receive_bandwidth); 737 UINT16_TO_STREAM(pp, max_latency); 738 UINT16_TO_STREAM(pp, voice); 739 UINT8_TO_STREAM(pp, retrans_effort); 740 UINT16_TO_STREAM(pp, packet_types); 741 742 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 743 } 744 745 void btsnd_hcic_accept_esco_conn(const RawAddress& bd_addr, 746 uint32_t transmit_bandwidth, 747 uint32_t receive_bandwidth, 748 uint16_t max_latency, uint16_t content_fmt, 749 uint8_t retrans_effort, 750 uint16_t packet_types) { 751 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 752 uint8_t* pp = (uint8_t*)(p + 1); 753 754 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO; 755 p->offset = 0; 756 757 UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION); 758 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO); 759 760 BDADDR_TO_STREAM(pp, bd_addr); 761 UINT32_TO_STREAM(pp, transmit_bandwidth); 762 UINT32_TO_STREAM(pp, receive_bandwidth); 763 UINT16_TO_STREAM(pp, max_latency); 764 UINT16_TO_STREAM(pp, content_fmt); 765 UINT8_TO_STREAM(pp, retrans_effort); 766 UINT16_TO_STREAM(pp, packet_types); 767 768 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 769 } 770 771 void btsnd_hcic_reject_esco_conn(const RawAddress& bd_addr, uint8_t reason) { 772 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 773 uint8_t* pp = (uint8_t*)(p + 1); 774 775 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO; 776 p->offset = 0; 777 778 UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION); 779 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO); 780 781 BDADDR_TO_STREAM(pp, bd_addr); 782 UINT8_TO_STREAM(pp, reason); 783 784 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 785 } 786 787 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period, 788 uint16_t min_hold_period) { 789 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 790 uint8_t* pp = (uint8_t*)(p + 1); 791 792 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE; 793 p->offset = 0; 794 795 UINT16_TO_STREAM(pp, HCI_HOLD_MODE); 796 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE); 797 798 UINT16_TO_STREAM(pp, handle); 799 UINT16_TO_STREAM(pp, max_hold_period); 800 UINT16_TO_STREAM(pp, min_hold_period); 801 802 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 803 } 804 805 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period, 806 uint16_t min_sniff_period, uint16_t sniff_attempt, 807 uint16_t sniff_timeout) { 808 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 809 uint8_t* pp = (uint8_t*)(p + 1); 810 811 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE; 812 p->offset = 0; 813 814 UINT16_TO_STREAM(pp, HCI_SNIFF_MODE); 815 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE); 816 817 UINT16_TO_STREAM(pp, handle); 818 UINT16_TO_STREAM(pp, max_sniff_period); 819 UINT16_TO_STREAM(pp, min_sniff_period); 820 UINT16_TO_STREAM(pp, sniff_attempt); 821 UINT16_TO_STREAM(pp, sniff_timeout); 822 823 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 824 } 825 826 void btsnd_hcic_exit_sniff_mode(uint16_t handle) { 827 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 828 uint8_t* pp = (uint8_t*)(p + 1); 829 830 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 831 p->offset = 0; 832 833 UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE); 834 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 835 836 UINT16_TO_STREAM(pp, handle); 837 838 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 839 } 840 841 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval, 842 uint16_t beacon_min_interval) { 843 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 844 uint8_t* pp = (uint8_t*)(p + 1); 845 846 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE; 847 p->offset = 0; 848 849 UINT16_TO_STREAM(pp, HCI_PARK_MODE); 850 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE); 851 852 UINT16_TO_STREAM(pp, handle); 853 UINT16_TO_STREAM(pp, beacon_max_interval); 854 UINT16_TO_STREAM(pp, beacon_min_interval); 855 856 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 857 } 858 859 void btsnd_hcic_exit_park_mode(uint16_t handle) { 860 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 861 uint8_t* pp = (uint8_t*)(p + 1); 862 863 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 864 p->offset = 0; 865 866 UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE); 867 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 868 869 UINT16_TO_STREAM(pp, handle); 870 871 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 872 } 873 874 static void btsnd_hcic_switch_role(const RawAddress& bd_addr, uint8_t role) { 875 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 876 uint8_t* pp = (uint8_t*)(p + 1); 877 878 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE; 879 p->offset = 0; 880 881 UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE); 882 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE); 883 884 BDADDR_TO_STREAM(pp, bd_addr); 885 UINT8_TO_STREAM(pp, role); 886 887 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 888 } 889 890 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) { 891 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 892 uint8_t* pp = (uint8_t*)(p + 1); 893 894 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET; 895 p->offset = 0; 896 UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS); 897 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET); 898 899 UINT16_TO_STREAM(pp, handle); 900 UINT16_TO_STREAM(pp, settings); 901 902 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 903 } 904 905 void btsnd_hcic_write_def_policy_set(uint16_t settings) { 906 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 907 uint8_t* pp = (uint8_t*)(p + 1); 908 909 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET; 910 p->offset = 0; 911 UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS); 912 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET); 913 914 UINT16_TO_STREAM(pp, settings); 915 916 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 917 } 918 919 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type, 920 uint8_t* filt_cond, uint8_t filt_cond_len) { 921 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 922 uint8_t* pp = (uint8_t*)(p + 1); 923 924 p->offset = 0; 925 926 UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER); 927 928 if (filt_type) { 929 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len); 930 UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len)); 931 932 UINT8_TO_STREAM(pp, filt_type); 933 UINT8_TO_STREAM(pp, filt_cond_type); 934 935 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) { 936 DEVCLASS_TO_STREAM(pp, filt_cond); 937 filt_cond += kDevClassLength; 938 DEVCLASS_TO_STREAM(pp, filt_cond); 939 filt_cond += kDevClassLength; 940 941 filt_cond_len -= (2 * kDevClassLength); 942 } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) { 943 BDADDR_TO_STREAM(pp, *((RawAddress*)filt_cond)); 944 filt_cond += BD_ADDR_LEN; 945 946 filt_cond_len -= BD_ADDR_LEN; 947 } 948 949 if (filt_cond_len) ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len); 950 } else { 951 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1); 952 UINT8_TO_STREAM(pp, 1); 953 954 UINT8_TO_STREAM(pp, filt_type); 955 } 956 957 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 958 } 959 960 void btsnd_hcic_write_pin_type(uint8_t type) { 961 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 962 uint8_t* pp = (uint8_t*)(p + 1); 963 964 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 965 p->offset = 0; 966 967 UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE); 968 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 969 970 UINT8_TO_STREAM(pp, type); 971 972 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 973 } 974 975 void btsnd_hcic_delete_stored_key(const RawAddress& bd_addr, 976 bool delete_all_flag) { 977 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 978 uint8_t* pp = (uint8_t*)(p + 1); 979 980 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY; 981 p->offset = 0; 982 983 UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY); 984 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY); 985 986 BDADDR_TO_STREAM(pp, bd_addr); 987 UINT8_TO_STREAM(pp, delete_all_flag); 988 989 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 990 } 991 992 void btsnd_hcic_change_name(BD_NAME name) { 993 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 994 uint8_t* pp = (uint8_t*)(p + 1); 995 uint16_t len = strlen((char*)name) + 1; 996 997 memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME); 998 999 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME; 1000 p->offset = 0; 1001 1002 UINT16_TO_STREAM(pp, HCI_CHANGE_LOCAL_NAME); 1003 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_NAME); 1004 1005 if (len > HCIC_PARAM_SIZE_CHANGE_NAME) len = HCIC_PARAM_SIZE_CHANGE_NAME; 1006 1007 ARRAY_TO_STREAM(pp, name, len); 1008 1009 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1010 } 1011 1012 void btsnd_hcic_read_name(void) { 1013 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1014 uint8_t* pp = (uint8_t*)(p + 1); 1015 1016 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 1017 p->offset = 0; 1018 1019 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME); 1020 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD); 1021 1022 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1023 } 1024 1025 void btsnd_hcic_write_page_tout(uint16_t timeout) { 1026 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1027 uint8_t* pp = (uint8_t*)(p + 1); 1028 1029 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 1030 p->offset = 0; 1031 1032 UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT); 1033 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 1034 1035 UINT16_TO_STREAM(pp, timeout); 1036 1037 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1038 } 1039 1040 void btsnd_hcic_write_scan_enable(uint8_t flag) { 1041 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1042 uint8_t* pp = (uint8_t*)(p + 1); 1043 1044 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1045 p->offset = 0; 1046 1047 UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE); 1048 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1049 1050 UINT8_TO_STREAM(pp, flag); 1051 1052 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1053 } 1054 1055 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) { 1056 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1057 uint8_t* pp = (uint8_t*)(p + 1); 1058 1059 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG; 1060 p->offset = 0; 1061 1062 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG); 1063 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG); 1064 1065 UINT16_TO_STREAM(pp, interval); 1066 UINT16_TO_STREAM(pp, window); 1067 1068 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1069 } 1070 1071 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) { 1072 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1073 uint8_t* pp = (uint8_t*)(p + 1); 1074 1075 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG; 1076 p->offset = 0; 1077 1078 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG); 1079 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG); 1080 1081 UINT16_TO_STREAM(pp, interval); 1082 UINT16_TO_STREAM(pp, window); 1083 1084 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1085 } 1086 1087 void btsnd_hcic_write_auth_enable(uint8_t flag) { 1088 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1089 uint8_t* pp = (uint8_t*)(p + 1); 1090 1091 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1092 p->offset = 0; 1093 1094 UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE); 1095 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1096 1097 UINT8_TO_STREAM(pp, flag); 1098 1099 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1100 } 1101 1102 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) { 1103 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1104 uint8_t* pp = (uint8_t*)(p + 1); 1105 1106 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3; 1107 p->offset = 0; 1108 1109 UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE); 1110 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3); 1111 1112 DEVCLASS_TO_STREAM(pp, dev_class); 1113 1114 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1115 } 1116 1117 void btsnd_hcic_write_voice_settings(uint16_t flags) { 1118 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1119 uint8_t* pp = (uint8_t*)(p + 1); 1120 1121 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 1122 p->offset = 0; 1123 1124 UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS); 1125 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 1126 1127 UINT16_TO_STREAM(pp, flags); 1128 1129 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1130 } 1131 1132 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) { 1133 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1134 uint8_t* pp = (uint8_t*)(p + 1); 1135 1136 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT; 1137 p->offset = 0; 1138 1139 UINT16_TO_STREAM(pp, HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT); 1140 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT); 1141 1142 UINT16_TO_STREAM(pp, handle); 1143 UINT16_TO_STREAM(pp, tout); 1144 1145 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1146 } 1147 1148 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) { 1149 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1150 uint8_t* pp = (uint8_t*)(p + 1); 1151 1152 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER; 1153 p->offset = 0; 1154 1155 UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL); 1156 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER); 1157 1158 UINT16_TO_STREAM(pp, handle); 1159 UINT8_TO_STREAM(pp, type); 1160 1161 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1162 } 1163 1164 void btsnd_hcic_write_link_super_tout(uint16_t handle, uint16_t timeout) { 1165 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1166 uint8_t* pp = (uint8_t*)(p + 1); 1167 1168 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT; 1169 p->offset = 0; 1170 1171 UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT); 1172 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT); 1173 1174 UINT16_TO_STREAM(pp, handle); 1175 UINT16_TO_STREAM(pp, timeout); 1176 1177 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1178 } 1179 1180 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) { 1181 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1182 uint8_t* pp = (uint8_t*)(p + 1); 1183 1184 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac); 1185 p->offset = 0; 1186 1187 UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP); 1188 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE); 1189 1190 UINT8_TO_STREAM(pp, num_cur_iac); 1191 1192 for (int i = 0; i < num_cur_iac; i++) LAP_TO_STREAM(pp, iac_lap[i]); 1193 1194 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1195 } 1196 1197 /****************************************** 1198 * Lisbon Features 1199 ******************************************/ 1200 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat, 1201 uint16_t min_remote_lat, 1202 uint16_t min_local_lat) { 1203 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1204 uint8_t* pp = (uint8_t*)(p + 1); 1205 1206 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE; 1207 p->offset = 0; 1208 1209 UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE); 1210 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE); 1211 1212 UINT16_TO_STREAM(pp, handle); 1213 UINT16_TO_STREAM(pp, max_lat); 1214 UINT16_TO_STREAM(pp, min_remote_lat); 1215 UINT16_TO_STREAM(pp, min_local_lat); 1216 1217 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1218 } 1219 1220 /**** Extended Inquiry Response Commands ****/ 1221 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) { 1222 BT_HDR* p = (BT_HDR*)buffer; 1223 uint8_t* pp = (uint8_t*)(p + 1); 1224 1225 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP; 1226 p->offset = 0; 1227 1228 UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE); 1229 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP); 1230 1231 UINT8_TO_STREAM(pp, fec_req); 1232 1233 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1234 } 1235 1236 void btsnd_hcic_io_cap_req_reply(const RawAddress& bd_addr, uint8_t capability, 1237 uint8_t oob_present, uint8_t auth_req) { 1238 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1239 uint8_t* pp = (uint8_t*)(p + 1); 1240 1241 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP; 1242 p->offset = 0; 1243 1244 UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY); 1245 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP); 1246 1247 BDADDR_TO_STREAM(pp, bd_addr); 1248 UINT8_TO_STREAM(pp, capability); 1249 UINT8_TO_STREAM(pp, oob_present); 1250 UINT8_TO_STREAM(pp, auth_req); 1251 1252 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1253 } 1254 1255 void btsnd_hcic_enhanced_set_up_synchronous_connection( 1256 uint16_t conn_handle, enh_esco_params_t* p_params) { 1257 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1258 uint8_t* pp = (uint8_t*)(p + 1); 1259 1260 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN; 1261 p->offset = 0; 1262 1263 UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION); 1264 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN); 1265 1266 UINT16_TO_STREAM(pp, conn_handle); 1267 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth); 1268 UINT32_TO_STREAM(pp, p_params->receive_bandwidth); 1269 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format); 1270 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id); 1271 UINT16_TO_STREAM(pp, 1272 p_params->transmit_coding_format.vendor_specific_codec_id); 1273 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format); 1274 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id); 1275 UINT16_TO_STREAM(pp, 1276 p_params->receive_coding_format.vendor_specific_codec_id); 1277 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size); 1278 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size); 1279 UINT32_TO_STREAM(pp, p_params->input_bandwidth); 1280 UINT32_TO_STREAM(pp, p_params->output_bandwidth); 1281 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format); 1282 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id); 1283 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id); 1284 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format); 1285 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id); 1286 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id); 1287 UINT16_TO_STREAM(pp, p_params->input_coded_data_size); 1288 UINT16_TO_STREAM(pp, p_params->output_coded_data_size); 1289 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format); 1290 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format); 1291 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position); 1292 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position); 1293 UINT8_TO_STREAM(pp, p_params->input_data_path); 1294 UINT8_TO_STREAM(pp, p_params->output_data_path); 1295 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size); 1296 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size); 1297 UINT16_TO_STREAM(pp, p_params->max_latency_ms); 1298 UINT16_TO_STREAM(pp, p_params->packet_types); 1299 UINT8_TO_STREAM(pp, p_params->retransmission_effort); 1300 1301 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1302 } 1303 1304 void btsnd_hcic_enhanced_accept_synchronous_connection( 1305 const RawAddress& bd_addr, enh_esco_params_t* p_params) { 1306 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1307 uint8_t* pp = (uint8_t*)(p + 1); 1308 1309 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN; 1310 p->offset = 0; 1311 1312 UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION); 1313 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN); 1314 1315 BDADDR_TO_STREAM(pp, bd_addr); 1316 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth); 1317 UINT32_TO_STREAM(pp, p_params->receive_bandwidth); 1318 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format); 1319 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id); 1320 UINT16_TO_STREAM(pp, 1321 p_params->transmit_coding_format.vendor_specific_codec_id); 1322 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format); 1323 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id); 1324 UINT16_TO_STREAM(pp, 1325 p_params->receive_coding_format.vendor_specific_codec_id); 1326 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size); 1327 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size); 1328 UINT32_TO_STREAM(pp, p_params->input_bandwidth); 1329 UINT32_TO_STREAM(pp, p_params->output_bandwidth); 1330 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format); 1331 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id); 1332 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id); 1333 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format); 1334 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id); 1335 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id); 1336 UINT16_TO_STREAM(pp, p_params->input_coded_data_size); 1337 UINT16_TO_STREAM(pp, p_params->output_coded_data_size); 1338 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format); 1339 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format); 1340 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position); 1341 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position); 1342 UINT8_TO_STREAM(pp, p_params->input_data_path); 1343 UINT8_TO_STREAM(pp, p_params->output_data_path); 1344 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size); 1345 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size); 1346 UINT16_TO_STREAM(pp, p_params->max_latency_ms); 1347 UINT16_TO_STREAM(pp, p_params->packet_types); 1348 UINT8_TO_STREAM(pp, p_params->retransmission_effort); 1349 1350 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1351 } 1352 1353 void btsnd_hcic_io_cap_req_neg_reply(const RawAddress& bd_addr, 1354 uint8_t err_code) { 1355 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1356 uint8_t* pp = (uint8_t*)(p + 1); 1357 1358 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY; 1359 p->offset = 0; 1360 1361 UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY); 1362 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY); 1363 1364 BDADDR_TO_STREAM(pp, bd_addr); 1365 UINT8_TO_STREAM(pp, err_code); 1366 1367 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1368 } 1369 1370 void btsnd_hcic_read_local_oob_data(void) { 1371 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1372 uint8_t* pp = (uint8_t*)(p + 1); 1373 1374 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB; 1375 p->offset = 0; 1376 1377 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA); 1378 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB); 1379 1380 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1381 } 1382 1383 void btsnd_hcic_read_local_oob_extended_data(void) { 1384 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1385 uint8_t* pp = (uint8_t*)(p + 1); 1386 1387 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED; 1388 p->offset = 0; 1389 1390 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_EXTENDED_DATA); 1391 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED); 1392 1393 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1394 } 1395 1396 void btsnd_hcic_user_conf_reply(const RawAddress& bd_addr, bool is_yes) { 1397 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1398 uint8_t* pp = (uint8_t*)(p + 1); 1399 1400 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY; 1401 p->offset = 0; 1402 1403 if (!is_yes) { 1404 /* Negative reply */ 1405 UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY); 1406 } else { 1407 /* Confirmation */ 1408 UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY); 1409 } 1410 1411 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY); 1412 1413 BDADDR_TO_STREAM(pp, bd_addr); 1414 1415 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1416 } 1417 1418 void btsnd_hcic_user_passkey_reply(const RawAddress& bd_addr, uint32_t value) { 1419 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1420 uint8_t* pp = (uint8_t*)(p + 1); 1421 1422 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY; 1423 p->offset = 0; 1424 1425 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY); 1426 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY); 1427 1428 BDADDR_TO_STREAM(pp, bd_addr); 1429 UINT32_TO_STREAM(pp, value); 1430 1431 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1432 } 1433 1434 void btsnd_hcic_user_passkey_neg_reply(const RawAddress& bd_addr) { 1435 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1436 uint8_t* pp = (uint8_t*)(p + 1); 1437 1438 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY; 1439 p->offset = 0; 1440 1441 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY); 1442 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY); 1443 1444 BDADDR_TO_STREAM(pp, bd_addr); 1445 1446 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1447 } 1448 1449 void btsnd_hcic_rem_oob_reply(const RawAddress& bd_addr, const Octet16& c, 1450 const Octet16& r) { 1451 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1452 uint8_t* pp = (uint8_t*)(p + 1); 1453 1454 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY; 1455 p->offset = 0; 1456 1457 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY); 1458 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY); 1459 1460 BDADDR_TO_STREAM(pp, bd_addr); 1461 ARRAY16_TO_STREAM(pp, c.data()); 1462 ARRAY16_TO_STREAM(pp, r.data()); 1463 1464 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1465 } 1466 1467 void btsnd_hcic_rem_oob_neg_reply(const RawAddress& bd_addr) { 1468 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1469 uint8_t* pp = (uint8_t*)(p + 1); 1470 1471 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY; 1472 p->offset = 0; 1473 1474 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY); 1475 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY); 1476 1477 BDADDR_TO_STREAM(pp, bd_addr); 1478 1479 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1480 } 1481 1482 /**** end of Simple Pairing Commands ****/ 1483 1484 /************************* 1485 * End of Lisbon Commands 1486 *************************/ 1487 1488 void btsnd_hcic_read_rssi(uint16_t handle) { 1489 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1490 uint8_t* pp = (uint8_t*)(p + 1); 1491 1492 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1493 p->offset = 0; 1494 1495 UINT16_TO_STREAM(pp, HCI_READ_RSSI); 1496 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1497 1498 UINT16_TO_STREAM(pp, handle); 1499 1500 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1501 } 1502 1503 static void read_encryption_key_size_complete( 1504 ReadEncKeySizeCb cb, uint8_t* return_parameters, 1505 uint16_t /* return_parameters_length */) { 1506 uint8_t status; 1507 uint16_t handle; 1508 uint8_t key_size; 1509 STREAM_TO_UINT8(status, return_parameters); 1510 STREAM_TO_UINT16(handle, return_parameters); 1511 STREAM_TO_UINT8(key_size, return_parameters); 1512 1513 std::move(cb).Run(status, handle, key_size); 1514 } 1515 1516 void btsnd_hcic_read_encryption_key_size(uint16_t handle, ReadEncKeySizeCb cb) { 1517 constexpr uint8_t len = 2; 1518 uint8_t param[len]; 1519 memset(param, 0, len); 1520 1521 uint8_t* p = param; 1522 UINT16_TO_STREAM(p, handle); 1523 1524 btu_hcif_send_cmd_with_cb(FROM_HERE, HCI_READ_ENCR_KEY_SIZE, param, len, 1525 base::Bind(&read_encryption_key_size_complete, base::Passed(&cb))); 1526 } 1527 1528 void btsnd_hcic_read_failed_contact_counter(uint16_t handle) { 1529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1530 uint8_t* pp = (uint8_t*)(p + 1); 1531 1532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1533 p->offset = 0; 1534 1535 UINT16_TO_STREAM(pp, HCI_READ_FAILED_CONTACT_COUNTER); 1536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1537 1538 UINT16_TO_STREAM(pp, handle); 1539 1540 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1541 } 1542 1543 void btsnd_hcic_enable_test_mode(void) { 1544 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1545 uint8_t* pp = (uint8_t*)(p + 1); 1546 1547 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 1548 p->offset = 0; 1549 1550 UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE); 1551 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD); 1552 1553 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1554 } 1555 1556 void btsnd_hcic_write_inqscan_type(uint8_t type) { 1557 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1558 uint8_t* pp = (uint8_t*)(p + 1); 1559 1560 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1561 p->offset = 0; 1562 1563 UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE); 1564 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1565 1566 UINT8_TO_STREAM(pp, type); 1567 1568 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1569 } 1570 1571 void btsnd_hcic_write_inquiry_mode(uint8_t mode) { 1572 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1573 uint8_t* pp = (uint8_t*)(p + 1); 1574 1575 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1576 p->offset = 0; 1577 1578 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE); 1579 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1580 1581 UINT8_TO_STREAM(pp, mode); 1582 1583 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1584 } 1585 1586 void btsnd_hcic_write_pagescan_type(uint8_t type) { 1587 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1588 uint8_t* pp = (uint8_t*)(p + 1); 1589 1590 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1591 p->offset = 0; 1592 1593 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE); 1594 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1595 1596 UINT8_TO_STREAM(pp, type); 1597 1598 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1599 } 1600 1601 static void btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB* p_vsc_cplt_cback, 1602 uint16_t opcode, uint8_t* data, 1603 uint16_t len) { 1604 /* If there was a callback address for vcs complete, call it */ 1605 if (p_vsc_cplt_cback) { 1606 tBTM_VSC_CMPL vcs_cplt_params; 1607 vcs_cplt_params.opcode = opcode; 1608 vcs_cplt_params.param_len = len; 1609 vcs_cplt_params.p_param_buf = data; 1610 /* Call the VSC complete callback function */ 1611 (*p_vsc_cplt_cback)(&vcs_cplt_params); 1612 } 1613 } 1614 1615 void btsnd_hcic_vendor_spec_cmd(uint16_t opcode, uint8_t len, uint8_t* p_data, 1616 tBTM_VSC_CMPL_CB* p_cmd_cplt_cback) { 1617 uint16_t v_opcode = HCI_GRP_VENDOR_SPECIFIC | opcode; 1618 1619 btu_hcif_send_cmd_with_cb( 1620 FROM_HERE, v_opcode, p_data, len, 1621 base::BindOnce(&btsnd_hcic_vendor_spec_complete, 1622 base::Unretained(p_cmd_cplt_cback), v_opcode)); 1623 } 1624 1625 void btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction, 1626 uint8_t data_path_id, 1627 std::vector<uint8_t> vendor_config) { 1628 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1629 uint8_t* pp = (uint8_t*)(p + 1); 1630 uint8_t size = static_cast<uint8_t>(vendor_config.size()); 1631 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size; 1632 p->offset = 0; 1633 1634 UINT16_TO_STREAM(pp, HCI_CONFIGURE_DATA_PATH); 1635 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size); 1636 UINT8_TO_STREAM(pp, data_path_direction); 1637 UINT8_TO_STREAM(pp, data_path_id); 1638 UINT8_TO_STREAM(pp, vendor_config.size()); 1639 if (size != 0) { 1640 ARRAY_TO_STREAM(pp, vendor_config.data(), size); 1641 } 1642 1643 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1644 } 1645 1646 namespace bluetooth::legacy::hci { 1647 class InterfaceImpl : public Interface { 1648 void Disconnect(uint16_t handle, uint8_t reason) const override { 1649 btsnd_hcic_disconnect(handle, reason); 1650 } 1651 void ChangeConnectionPacketType(uint16_t handle, 1652 uint16_t packet_types) const override { 1653 btsnd_hcic_change_conn_type(handle, packet_types); 1654 } 1655 void StartRoleSwitch(const RawAddress& bd_addr, uint8_t role) const override { 1656 btsnd_hcic_switch_role(bd_addr, role); 1657 } 1658 void ConfigureDataPath(hci_data_direction_t data_path_direction, 1659 uint8_t data_path_id, 1660 std::vector<uint8_t> vendor_config) const override { 1661 btsnd_hcic_configure_data_path(data_path_direction, data_path_id, 1662 vendor_config); 1663 } 1664 void SendVendorSpecificCmd(unsigned short opcode, 1665 unsigned char len, unsigned char* param, void (*cb)(tBTM_VSC_CMPL*)) const override { 1666 btsnd_hcic_vendor_spec_cmd(opcode, len, param, cb); 1667 } 1668 }; 1669 1670 namespace { 1671 const InterfaceImpl interface_; 1672 } 1673 1674 const Interface& GetInterface() { return interface_; } 1675 } // namespace bluetooth::legacy::hci 1676 1677 void btsnd_hcic_flow_spec(uint16_t handle, uint8_t unused, uint8_t direction, 1678 uint8_t service_type, uint32_t token_rate, 1679 uint32_t token_size, uint32_t peak, uint32_t latency){ 1680 1681 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1682 uint8_t* pp = (uint8_t*)(p + 1); 1683 1684 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_FLOW_SPECIFICATION; 1685 p->offset = 0; 1686 1687 UINT16_TO_STREAM(pp, HCI_FLOW_SPECIFICATION); 1688 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_FLOW_SPECIFICATION); 1689 1690 UINT16_TO_STREAM(pp, handle); 1691 UINT8_TO_STREAM(pp, unused); 1692 UINT8_TO_STREAM(pp, direction); 1693 UINT8_TO_STREAM(pp, service_type); 1694 UINT32_TO_STREAM(pp, token_rate); 1695 UINT32_TO_STREAM(pp, token_size); 1696 UINT32_TO_STREAM(pp, peak); 1697 UINT32_TO_STREAM(pp, latency); 1698 1699 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1700 }
07-18
#include <base/functional/bind.h> 27 #include <base/functional/callback_forward.h> 28 #include <string.h> 29 30 #include "device/include/esco_parameters.h" 31 #include "hcidefs.h" 32 #include "hcimsgs.h" 33 #include "internal_include/bt_target.h" 34 #include "main/shim/acl_api.h" 35 #include "osi/include/allocator.h" 36 #include "stack/include/bt_dev_class.h" 37 #include "stack/include/bt_hdr.h" 38 #include "stack/include/bt_lap.h" 39 #include "stack/include/bt_octets.h" 40 #include "stack/include/bt_types.h" 41 #include "stack/include/btu_hcif.h" 42 #include "types/raw_address.h" 43 44 /* Message by message.... */ 45 46 #define HCIC_PARAM_SIZE_INQUIRY 5 47 48 #define HCIC_INQ_INQ_LAP_OFF 0 49 #define HCIC_INQ_DUR_OFF 3 50 #define HCIC_INQ_RSP_CNT_OFF 4 51 52 /* Periodic Inquiry Mode */ 53 #define HCIC_PARAM_SIZE_PER_INQ_MODE 9 54 55 #define HCI_PER_INQ_MAX_INTRVL_OFF 0 56 #define HCI_PER_INQ_MIN_INTRVL_OFF 2 57 #define HCI_PER_INQ_INQ_LAP_OFF 4 58 #define HCI_PER_INQ_DURATION_OFF 7 59 #define HCI_PER_INQ_RSP_CNT_OFF 8 60 /* Periodic Inquiry Mode */ 61 62 /* Exit Periodic Inquiry Mode */ 63 #define HCIC_PARAM_SIZE_EXIT_PER_INQ 0 64 65 /* Create Connection */ 66 #define HCIC_PARAM_SIZE_CREATE_CONN 13 67 68 #define HCIC_CR_CONN_BD_ADDR_OFF 0 69 #define HCIC_CR_CONN_PKT_TYPES_OFF 6 70 #define HCIC_CR_CONN_REP_MODE_OFF 8 71 #define HCIC_CR_CONN_PAGE_SCAN_MODE_OFF 9 72 #define HCIC_CR_CONN_CLK_OFF_OFF 10 73 #define HCIC_CR_CONN_ALLOW_SWITCH_OFF 12 74 /* Create Connection */ 75 76 /* Disconnect */ 77 #define HCIC_PARAM_SIZE_DISCONNECT 3 78 79 #define HCI_DISC_HANDLE_OFF 0 80 #define HCI_DISC_REASON_OFF 2 81 /* Disconnect */ 82 83 /* Add SCO Connection */ 84 #define HCIC_PARAM_SIZE_ADD_SCO_CONN 4 85 86 #define HCI_ADD_SCO_HANDLE_OFF 0 87 #define HCI_ADD_SCO_PACKET_TYPES_OFF 2 88 /* Add SCO Connection */ 89 90 /* Create Connection Cancel */ 91 #define HCIC_PARAM_SIZE_CREATE_CONN_CANCEL 6 92 93 #define HCIC_CR_CONN_CANCEL_BD_ADDR_OFF 0 94 /* Create Connection Cancel */ 95 96 /* Accept Connection Request */ 97 #define HCIC_PARAM_SIZE_ACCEPT_CONN 7 98 99 #define HCI_ACC_CONN_BD_ADDR_OFF 0 100 #define HCI_ACC_CONN_ROLE_OFF 6 101 /* Accept Connection Request */ 102 103 /* Reject Connection Request */ 104 #define HCIC_PARAM_SIZE_REJECT_CONN 7 105 106 #define HCI_REJ_CONN_BD_ADDR_OFF 0 107 #define HCI_REJ_CONN_REASON_OFF 6 108 /* Reject Connection Request */ 109 110 /* Link Key Request Reply */ 111 #define HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY 22 112 113 #define HCI_LINK_KEY_REPLY_BD_ADDR_OFF 0 114 #define HCI_LINK_KEY_REPLY_LINK_KEY_OFF 6 115 /* Link Key Request Reply */ 116 117 /* Link Key Request Neg Reply */ 118 #define HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY 6 119 120 #define HCI_LINK_KEY_NEG_REP_BD_ADR_OFF 0 121 /* Link Key Request Neg Reply */ 122 123 /* PIN Code Request Reply */ 124 #define HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY 23 125 126 #define HCI_PIN_CODE_REPLY_BD_ADDR_OFF 0 127 #define HCI_PIN_CODE_REPLY_PIN_LEN_OFF 6 128 #define HCI_PIN_CODE_REPLY_PIN_CODE_OFF 7 129 /* PIN Code Request Reply */ 130 131 /* Link Key Request Neg Reply */ 132 #define HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY 6 133 134 #define HCI_PIN_CODE_NEG_REP_BD_ADR_OFF 0 135 /* Link Key Request Neg Reply */ 136 137 /* Change Connection Type */ 138 #define HCIC_PARAM_SIZE_CHANGE_CONN_TYPE 4 139 140 #define HCI_CHNG_PKT_TYPE_HANDLE_OFF 0 141 #define HCI_CHNG_PKT_TYPE_PKT_TYPE_OFF 2 142 /* Change Connection Type */ 143 144 #define HCIC_PARAM_SIZE_CMD_HANDLE 2 145 146 #define HCI_CMD_HANDLE_HANDLE_OFF 0 147 148 /* Set Connection Encryption */ 149 #define HCIC_PARAM_SIZE_SET_CONN_ENCRYPT 3 150 151 #define HCI_SET_ENCRYPT_HANDLE_OFF 0 152 #define HCI_SET_ENCRYPT_ENABLE_OFF 2 153 /* Set Connection Encryption */ 154 155 /* Remote Name Request */ 156 #define HCIC_PARAM_SIZE_RMT_NAME_REQ 10 157 158 #define HCI_RMT_NAME_BD_ADDR_OFF 0 159 #define HCI_RMT_NAME_REP_MODE_OFF 6 160 #define HCI_RMT_NAME_PAGE_SCAN_MODE_OFF 7 161 #define HCI_RMT_NAME_CLK_OFF_OFF 8 162 /* Remote Name Request */ 163 164 /* Remote Name Request Cancel */ 165 #define HCIC_PARAM_SIZE_RMT_NAME_REQ_CANCEL 6 166 167 #define HCI_RMT_NAME_CANCEL_BD_ADDR_OFF 0 168 /* Remote Name Request Cancel */ 169 170 /* Remote Extended Features */ 171 #define HCIC_PARAM_SIZE_RMT_EXT_FEATURES 3 172 173 #define HCI_RMT_EXT_FEATURES_HANDLE_OFF 0 174 #define HCI_RMT_EXT_FEATURES_PAGE_NUM_OFF 2 175 /* Remote Extended Features */ 176 177 #define HCIC_PARAM_SIZE_SETUP_ESCO 17 178 179 #define HCI_SETUP_ESCO_HANDLE_OFF 0 180 #define HCI_SETUP_ESCO_TX_BW_OFF 2 181 #define HCI_SETUP_ESCO_RX_BW_OFF 6 182 #define HCI_SETUP_ESCO_MAX_LAT_OFF 10 183 #define HCI_SETUP_ESCO_VOICE_OFF 12 184 #define HCI_SETUP_ESCO_RETRAN_EFF_OFF 14 185 #define HCI_SETUP_ESCO_PKT_TYPES_OFF 15 186 187 #define HCIC_PARAM_SIZE_ACCEPT_ESCO 21 188 189 #define HCI_ACCEPT_ESCO_BDADDR_OFF 0 190 #define HCI_ACCEPT_ESCO_TX_BW_OFF 6 191 #define HCI_ACCEPT_ESCO_RX_BW_OFF 10 192 #define HCI_ACCEPT_ESCO_MAX_LAT_OFF 14 193 #define HCI_ACCEPT_ESCO_VOICE_OFF 16 194 #define HCI_ACCEPT_ESCO_RETRAN_EFF_OFF 18 195 #define HCI_ACCEPT_ESCO_PKT_TYPES_OFF 19 196 197 #define HCIC_PARAM_SIZE_REJECT_ESCO 7 198 199 #define HCI_REJECT_ESCO_BDADDR_OFF 0 200 #define HCI_REJECT_ESCO_REASON_OFF 6 201 202 /* Hold Mode */ 203 #define HCIC_PARAM_SIZE_HOLD_MODE 6 204 205 #define HCI_HOLD_MODE_HANDLE_OFF 0 206 #define HCI_HOLD_MODE_MAX_PER_OFF 2 207 #define HCI_HOLD_MODE_MIN_PER_OFF 4 208 /* Hold Mode */ 209 210 /* Sniff Mode */ 211 #define HCIC_PARAM_SIZE_SNIFF_MODE 10 212 213 #define HCI_SNIFF_MODE_HANDLE_OFF 0 214 #define HCI_SNIFF_MODE_MAX_PER_OFF 2 215 #define HCI_SNIFF_MODE_MIN_PER_OFF 4 216 #define HCI_SNIFF_MODE_ATTEMPT_OFF 6 217 #define HCI_SNIFF_MODE_TIMEOUT_OFF 8 218 /* Sniff Mode */ 219 220 /* Park Mode */ 221 #define HCIC_PARAM_SIZE_PARK_MODE 6 222 223 #define HCI_PARK_MODE_HANDLE_OFF 0 224 #define HCI_PARK_MODE_MAX_PER_OFF 2 225 #define HCI_PARK_MODE_MIN_PER_OFF 4 226 /* Park Mode */ 227 228 /* QoS Setup */ 229 #define HCIC_PARAM_SIZE_QOS_SETUP 20 230 231 #define HCI_QOS_HANDLE_OFF 0 232 #define HCI_QOS_FLAGS_OFF 2 233 #define HCI_QOS_SERVICE_TYPE_OFF 3 234 #define HCI_QOS_TOKEN_RATE_OFF 4 235 #define HCI_QOS_PEAK_BANDWIDTH_OFF 8 236 #define HCI_QOS_LATENCY_OFF 12 237 #define HCI_QOS_DELAY_VAR_OFF 16 238 /* QoS Setup */ 239 240 #define HCIC_PARAM_SIZE_SWITCH_ROLE 7 241 242 #define HCI_SWITCH_BD_ADDR_OFF 0 243 #define HCI_SWITCH_ROLE_OFF 6 244 /* Switch Role Request */ 245 246 /* Write Policy Settings */ 247 #define HCIC_PARAM_SIZE_WRITE_POLICY_SET 4 248 249 #define HCI_WRITE_POLICY_HANDLE_OFF 0 250 #define HCI_WRITE_POLICY_SETTINGS_OFF 2 251 /* Write Policy Settings */ 252 253 /* Write Default Policy Settings */ 254 #define HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET 2 255 256 #define HCI_WRITE_DEF_POLICY_SETTINGS_OFF 0 257 /* Write Default Policy Settings */ 258 259 #define HCIC_PARAM_SIZE_SNIFF_SUB_RATE 8 260 261 #define HCI_SNIFF_SUB_RATE_HANDLE_OFF 0 262 #define HCI_SNIFF_SUB_RATE_MAX_LAT_OFF 2 263 #define HCI_SNIFF_SUB_RATE_MIN_REM_LAT_OFF 4 264 #define HCI_SNIFF_SUB_RATE_MIN_LOC_LAT_OFF 6 265 /* Sniff Subrating */ 266 267 /* Extended Inquiry Response */ 268 #define HCIC_PARAM_SIZE_EXT_INQ_RESP 241 269 270 #define HCIC_EXT_INQ_RESP_FEC_OFF 0 271 #define HCIC_EXT_INQ_RESP_RESPONSE 1 272 /* IO Capabilities Response */ 273 #define HCIC_PARAM_SIZE_IO_CAP_RESP 9 274 275 #define HCI_IO_CAP_BD_ADDR_OFF 0 276 #define HCI_IO_CAPABILITY_OFF 6 277 #define HCI_IO_CAP_OOB_DATA_OFF 7 278 #define HCI_IO_CAP_AUTH_REQ_OFF 8 279 280 /* IO Capabilities Req Neg Reply */ 281 #define HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY 7 282 283 #define HCI_IO_CAP_NR_BD_ADDR_OFF 0 284 #define HCI_IO_CAP_NR_ERR_CODE 6 285 286 /* Read Local OOB Data */ 287 #define HCIC_PARAM_SIZE_R_LOCAL_OOB 0 288 289 /* Read Local OOB Extended Data */ 290 #define HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED 0 291 292 #define HCIC_PARAM_SIZE_UCONF_REPLY 6 293 294 #define HCI_USER_CONF_BD_ADDR_OFF 0 295 296 #define HCIC_PARAM_SIZE_U_PKEY_REPLY 10 297 298 #define HCI_USER_PASSKEY_BD_ADDR_OFF 0 299 #define HCI_USER_PASSKEY_VALUE_OFF 6 300 301 #define HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY 6 302 303 #define HCI_USER_PASSKEY_NEG_BD_ADDR_OFF 0 304 305 /* Remote OOB Data Request Reply */ 306 #define HCIC_PARAM_SIZE_REM_OOB_REPLY 38 307 308 #define HCI_REM_OOB_DATA_BD_ADDR_OFF 0 309 #define HCI_REM_OOB_DATA_C_OFF 6 310 #define HCI_REM_OOB_DATA_R_OFF 22 311 312 /* Remote OOB Data Request Negative Reply */ 313 #define HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY 6 314 315 #define HCI_REM_OOB_DATA_NEG_BD_ADDR_OFF 0 316 317 /* Read Tx Power Level */ 318 #define HCIC_PARAM_SIZE_R_TX_POWER 0 319 320 /* Read Default Erroneous Data Reporting */ 321 #define HCIC_PARAM_SIZE_R_ERR_DATA_RPT 0 322 323 #define HCIC_PARAM_SIZE_SEND_KEYPRESS_NOTIF 7 324 325 #define HCI_SEND_KEYPRESS_NOTIF_BD_ADDR_OFF 0 326 #define HCI_SEND_KEYPRESS_NOTIF_NOTIF_OFF 6 327 328 /**** end of Simple Pairing Commands ****/ 329 330 #define HCIC_PARAM_SIZE_SET_EVT_FILTER 9 331 332 #define HCI_FILT_COND_FILT_TYPE_OFF 0 333 #define HCI_FILT_COND_COND_TYPE_OFF 1 334 #define HCI_FILT_COND_FILT_OFF 2 335 /* Set Event Filter */ 336 337 /* Delete Stored Key */ 338 #define HCIC_PARAM_SIZE_DELETE_STORED_KEY 7 339 340 #define HCI_DELETE_KEY_BD_ADDR_OFF 0 341 #define HCI_DELETE_KEY_ALL_FLAG_OFF 6 342 /* Delete Stored Key */ 343 344 /* Change Local Name */ 345 #define HCIC_PARAM_SIZE_CHANGE_NAME BD_NAME_LEN 346 347 #define HCI_CHANGE_NAME_NAME_OFF 0 348 /* Change Local Name */ 349 350 #define HCIC_PARAM_SIZE_READ_CMD 0 351 352 #define HCIC_PARAM_SIZE_WRITE_PARAM1 1 353 354 #define HCIC_WRITE_PARAM1_PARAM_OFF 0 355 356 #define HCIC_PARAM_SIZE_WRITE_PARAM2 2 357 358 #define HCIC_WRITE_PARAM2_PARAM_OFF 0 359 360 #define HCIC_PARAM_SIZE_WRITE_PARAM3 3 361 362 #define HCIC_WRITE_PARAM3_PARAM_OFF 0 363 364 #define HCIC_PARAM_SIZE_SET_AFH_CHANNELS 10 365 366 #define HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN 59 367 #define HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN 63 368 369 #define HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG 4 370 371 #define HCI_SCAN_CFG_INTERVAL_OFF 0 372 #define HCI_SCAN_CFG_WINDOW_OFF 2 373 /* Write Page Scan Activity */ 374 375 /* Write Inquiry Scan Activity */ 376 #define HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG 4 377 378 #define HCI_SCAN_CFG_INTERVAL_OFF 0 379 #define HCI_SCAN_CFG_WINDOW_OFF 2 380 /* Write Inquiry Scan Activity */ 381 382 /* Host Controller to Host flow control */ 383 #define HCI_HOST_FLOW_CTRL_OFF 0 384 #define HCI_HOST_FLOW_CTRL_ACL_ON 1 385 #define HCI_HOST_FLOW_CTRL_SCO_ON 2 386 #define HCI_HOST_FLOW_CTRL_BOTH_ON 3 387 388 #define HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT 4 389 390 #define HCI_FLUSH_TOUT_HANDLE_OFF 0 391 #define HCI_FLUSH_TOUT_TOUT_OFF 2 392 393 #define HCIC_PARAM_SIZE_READ_TX_POWER 3 394 395 #define HCI_READ_TX_POWER_HANDLE_OFF 0 396 #define HCI_READ_TX_POWER_TYPE_OFF 2 397 398 /* Read transmit power level parameter */ 399 #define HCI_READ_CURRENT 0x00 400 #define HCI_READ_MAXIMUM 0x01 401 402 #define HCIC_PARAM_SIZE_NUM_PKTS_DONE_SIZE sizeof(btmsg_hcic_num_pkts_done_t) 403 404 #define MAX_DATA_HANDLES 10 405 406 #define HCI_PKTS_DONE_NUM_HANDLES_OFF 0 407 #define HCI_PKTS_DONE_HANDLE_OFF 1 408 #define HCI_PKTS_DONE_NUM_PKTS_OFF 3 409 410 #define HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT 4 411 412 #define HCI_LINK_SUPER_TOUT_HANDLE_OFF 0 413 #define HCI_LINK_SUPER_TOUT_TOUT_OFF 2 414 /* Write Link Supervision Timeout */ 415 416 #define MAX_IAC_LAPS 0x40 417 418 #define HCI_WRITE_IAC_LAP_NUM_OFF 0 419 #define HCI_WRITE_IAC_LAP_LAP_OFF 1 420 /* Write Current IAC LAP */ 421 422 #define HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH 3 423 424 /******************************************************************************* 425 * BLE Commands 426 * Note: "local_controller_id" is for transport, not counted in HCI 427 * message size 428 ******************************************************************************/ 429 #define HCIC_BLE_RAND_DI_SIZE 8 430 #define HCIC_BLE_IRK_SIZE 16 431 432 #define HCIC_PARAM_SIZE_SET_USED_FEAT_CMD 8 433 #define HCIC_PARAM_SIZE_WRITE_RANDOM_ADDR_CMD 6 434 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_PARAMS 15 435 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_RSP 31 436 #define HCIC_PARAM_SIZE_WRITE_ADV_ENABLE 1 437 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_PARAM 7 438 #define HCIC_PARAM_SIZE_BLE_WRITE_SCAN_ENABLE 2 439 #define HCIC_PARAM_SIZE_BLE_CREATE_LL_CONN 25 440 #define HCIC_PARAM_SIZE_BLE_CREATE_CONN_CANCEL 0 441 #define HCIC_PARAM_SIZE_CLEAR_ACCEPTLIST 0 442 #define HCIC_PARAM_SIZE_ADD_ACCEPTLIST 7 443 #define HCIC_PARAM_SIZE_REMOVE_ACCEPTLIST 7 444 #define HCIC_PARAM_SIZE_BLE_UPD_LL_CONN_PARAMS 14 445 #define HCIC_PARAM_SIZE_SET_HOST_CHNL_CLASS 5 446 #define HCIC_PARAM_SIZE_READ_CHNL_MAP 2 447 #define HCIC_PARAM_SIZE_BLE_READ_REMOTE_FEAT 2 448 #define HCIC_PARAM_SIZE_BLE_ENCRYPT 32 449 #define HCIC_PARAM_SIZE_WRITE_LE_HOST_SUPPORTED 2 450 451 #define HCIC_BLE_RAND_DI_SIZE 8 452 #define HCIC_BLE_ENCRYPT_KEY_SIZE 16 453 #define HCIC_PARAM_SIZE_BLE_START_ENC \ 454 (4 + HCIC_BLE_RAND_DI_SIZE + HCIC_BLE_ENCRYPT_KEY_SIZE) 455 #define HCIC_PARAM_SIZE_LTK_REQ_REPLY (2 + HCIC_BLE_ENCRYPT_KEY_SIZE) 456 #define HCIC_PARAM_SIZE_LTK_REQ_NEG_REPLY 2 457 #define HCIC_BLE_CHNL_MAP_SIZE 5 458 #define HCIC_PARAM_SIZE_BLE_WRITE_ADV_DATA 31 459 460 #define HCIC_PARAM_SIZE_BLE_ADD_DEV_RESOLVING_LIST (7 + HCIC_BLE_IRK_SIZE * 2) 461 #define HCIC_PARAM_SIZE_BLE_RM_DEV_RESOLVING_LIST 7 462 #define HCIC_PARAM_SIZE_BLE_SET_PRIVACY_MODE 8 463 #define HCIC_PARAM_SIZE_BLE_CLEAR_RESOLVING_LIST 0 464 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVING_LIST_SIZE 0 465 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_PEER 7 466 #define HCIC_PARAM_SIZE_BLE_READ_RESOLVABLE_ADDR_LOCAL 7 467 #define HCIC_PARAM_SIZE_BLE_SET_ADDR_RESOLUTION_ENABLE 1 468 #define HCIC_PARAM_SIZE_BLE_SET_RAND_PRIV_ADDR_TIMOUT 2 469 470 #define HCIC_PARAM_SIZE_BLE_READ_PHY 2 471 #define HCIC_PARAM_SIZE_BLE_SET_DEFAULT_PHY 3 472 #define HCIC_PARAM_SIZE_BLE_SET_PHY 7 473 #define HCIC_PARAM_SIZE_BLE_ENH_RX_TEST 3 474 #define HCIC_PARAM_SIZE_BLE_ENH_TX_TEST 4 475 476 #define HCIC_PARAM_SIZE_BLE_SET_DATA_LENGTH 6 477 #define HCIC_PARAM_SIZE_BLE_WRITE_EXTENDED_SCAN_PARAM 11 478 479 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_REPLY 14 480 #define HCIC_PARAM_SIZE_BLE_RC_PARAM_REQ_NEG_REPLY 3 481 482 static void btsnd_hcic_disconnect(uint16_t handle, uint8_t reason) { 483 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 484 uint8_t* pp = (uint8_t*)(p + 1); 485 486 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DISCONNECT; 487 p->offset = 0; 488 489 UINT16_TO_STREAM(pp, HCI_DISCONNECT); 490 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DISCONNECT); 491 UINT16_TO_STREAM(pp, handle); 492 UINT8_TO_STREAM(pp, reason); 493 494 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 495 } 496 497 void btsnd_hcic_add_SCO_conn(uint16_t handle, uint16_t packet_types) { 498 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 499 uint8_t* pp = (uint8_t*)(p + 1); 500 501 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ADD_SCO_CONN; 502 p->offset = 0; 503 504 UINT16_TO_STREAM(pp, HCI_ADD_SCO_CONNECTION); 505 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ADD_SCO_CONN); 506 507 UINT16_TO_STREAM(pp, handle); 508 UINT16_TO_STREAM(pp, packet_types); 509 510 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 511 } 512 513 void btsnd_hcic_create_conn_cancel(const RawAddress& dest) { 514 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 515 uint8_t* pp = (uint8_t*)(p + 1); 516 517 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CREATE_CONN_CANCEL; 518 p->offset = 0; 519 520 UINT16_TO_STREAM(pp, HCI_CREATE_CONNECTION_CANCEL); 521 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CREATE_CONN_CANCEL); 522 523 BDADDR_TO_STREAM(pp, dest); 524 525 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 526 } 527 528 void btsnd_hcic_accept_conn(const RawAddress& dest, uint8_t role) { 529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 530 uint8_t* pp = (uint8_t*)(p + 1); 531 532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_CONN; 533 p->offset = 0; 534 535 UINT16_TO_STREAM(pp, HCI_ACCEPT_CONNECTION_REQUEST); 536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_CONN); 537 BDADDR_TO_STREAM(pp, dest); 538 UINT8_TO_STREAM(pp, role); 539 540 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 541 } 542 543 void btsnd_hcic_reject_conn(const RawAddress& dest, uint8_t reason) { 544 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 545 uint8_t* pp = (uint8_t*)(p + 1); 546 547 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_CONN; 548 p->offset = 0; 549 550 UINT16_TO_STREAM(pp, HCI_REJECT_CONNECTION_REQUEST); 551 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_CONN); 552 553 BDADDR_TO_STREAM(pp, dest); 554 UINT8_TO_STREAM(pp, reason); 555 556 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 557 } 558 559 void btsnd_hcic_link_key_req_reply(const RawAddress& bd_addr, 560 const LinkKey& link_key) { 561 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 562 uint8_t* pp = (uint8_t*)(p + 1); 563 564 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY; 565 p->offset = 0; 566 567 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_REPLY); 568 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_REQ_REPLY); 569 570 BDADDR_TO_STREAM(pp, bd_addr); 571 ARRAY16_TO_STREAM(pp, link_key.data()); 572 573 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 574 } 575 576 void btsnd_hcic_link_key_neg_reply(const RawAddress& bd_addr) { 577 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 578 uint8_t* pp = (uint8_t*)(p + 1); 579 580 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY; 581 p->offset = 0; 582 583 UINT16_TO_STREAM(pp, HCI_LINK_KEY_REQUEST_NEG_REPLY); 584 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_LINK_KEY_NEG_REPLY); 585 586 BDADDR_TO_STREAM(pp, bd_addr); 587 588 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 589 } 590 591 void btsnd_hcic_pin_code_req_reply(const RawAddress& bd_addr, 592 uint8_t pin_code_len, PIN_CODE pin_code) { 593 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 594 uint8_t* pp = (uint8_t*)(p + 1); 595 int i; 596 597 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY; 598 p->offset = 0; 599 600 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_REPLY); 601 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_REQ_REPLY); 602 603 BDADDR_TO_STREAM(pp, bd_addr); 604 UINT8_TO_STREAM(pp, pin_code_len); 605 606 for (i = 0; i < pin_code_len; i++) *pp++ = *pin_code++; 607 608 for (; i < PIN_CODE_LEN; i++) *pp++ = 0; 609 610 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 611 } 612 613 void btsnd_hcic_pin_code_neg_reply(const RawAddress& bd_addr) { 614 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 615 uint8_t* pp = (uint8_t*)(p + 1); 616 617 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY; 618 p->offset = 0; 619 620 UINT16_TO_STREAM(pp, HCI_PIN_CODE_REQUEST_NEG_REPLY); 621 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PIN_CODE_NEG_REPLY); 622 623 BDADDR_TO_STREAM(pp, bd_addr); 624 625 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 626 } 627 628 void btsnd_hcic_change_conn_type(uint16_t handle, uint16_t packet_types) { 629 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 630 uint8_t* pp = (uint8_t*)(p + 1); 631 632 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_CONN_TYPE; 633 p->offset = 0; 634 635 UINT16_TO_STREAM(pp, HCI_CHANGE_CONN_PACKET_TYPE); 636 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_CONN_TYPE); 637 638 UINT16_TO_STREAM(pp, handle); 639 UINT16_TO_STREAM(pp, packet_types); 640 641 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 642 } 643 644 void btsnd_hcic_auth_request(uint16_t handle) { 645 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 646 uint8_t* pp = (uint8_t*)(p + 1); 647 648 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 649 p->offset = 0; 650 651 UINT16_TO_STREAM(pp, HCI_AUTHENTICATION_REQUESTED); 652 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 653 654 UINT16_TO_STREAM(pp, handle); 655 656 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 657 } 658 659 void btsnd_hcic_set_conn_encrypt(uint16_t handle, bool enable) { 660 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 661 uint8_t* pp = (uint8_t*)(p + 1); 662 663 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SET_CONN_ENCRYPT; 664 p->offset = 0; 665 666 UINT16_TO_STREAM(pp, HCI_SET_CONN_ENCRYPTION); 667 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SET_CONN_ENCRYPT); 668 669 UINT16_TO_STREAM(pp, handle); 670 UINT8_TO_STREAM(pp, enable); 671 672 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 673 } 674 675 void btsnd_hcic_rmt_ext_features(uint16_t handle, uint8_t page_num) { 676 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 677 uint8_t* pp = (uint8_t*)(p + 1); 678 679 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_RMT_EXT_FEATURES; 680 p->offset = 0; 681 682 UINT16_TO_STREAM(pp, HCI_READ_RMT_EXT_FEATURES); 683 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_RMT_EXT_FEATURES); 684 685 UINT16_TO_STREAM(pp, handle); 686 UINT8_TO_STREAM(pp, page_num); 687 688 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 689 } 690 691 void btsnd_hcic_rmt_ver_req(uint16_t handle) { 692 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 693 uint8_t* pp = (uint8_t*)(p + 1); 694 695 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 696 p->offset = 0; 697 698 UINT16_TO_STREAM(pp, HCI_READ_RMT_VERSION_INFO); 699 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 700 701 UINT16_TO_STREAM(pp, handle); 702 703 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 704 } 705 706 void btsnd_hcic_read_rmt_clk_offset(uint16_t handle) { 707 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 708 uint8_t* pp = (uint8_t*)(p + 1); 709 710 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 711 p->offset = 0; 712 713 UINT16_TO_STREAM(pp, HCI_READ_RMT_CLOCK_OFFSET); 714 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 715 716 UINT16_TO_STREAM(pp, handle); 717 718 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 719 } 720 721 void btsnd_hcic_setup_esco_conn(uint16_t handle, uint32_t transmit_bandwidth, 722 uint32_t receive_bandwidth, 723 uint16_t max_latency, uint16_t voice, 724 uint8_t retrans_effort, uint16_t packet_types) { 725 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 726 uint8_t* pp = (uint8_t*)(p + 1); 727 728 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SETUP_ESCO; 729 p->offset = 0; 730 731 UINT16_TO_STREAM(pp, HCI_SETUP_ESCO_CONNECTION); 732 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SETUP_ESCO); 733 734 UINT16_TO_STREAM(pp, handle); 735 UINT32_TO_STREAM(pp, transmit_bandwidth); 736 UINT32_TO_STREAM(pp, receive_bandwidth); 737 UINT16_TO_STREAM(pp, max_latency); 738 UINT16_TO_STREAM(pp, voice); 739 UINT8_TO_STREAM(pp, retrans_effort); 740 UINT16_TO_STREAM(pp, packet_types); 741 742 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 743 } 744 745 void btsnd_hcic_accept_esco_conn(const RawAddress& bd_addr, 746 uint32_t transmit_bandwidth, 747 uint32_t receive_bandwidth, 748 uint16_t max_latency, uint16_t content_fmt, 749 uint8_t retrans_effort, 750 uint16_t packet_types) { 751 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 752 uint8_t* pp = (uint8_t*)(p + 1); 753 754 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ACCEPT_ESCO; 755 p->offset = 0; 756 757 UINT16_TO_STREAM(pp, HCI_ACCEPT_ESCO_CONNECTION); 758 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ACCEPT_ESCO); 759 760 BDADDR_TO_STREAM(pp, bd_addr); 761 UINT32_TO_STREAM(pp, transmit_bandwidth); 762 UINT32_TO_STREAM(pp, receive_bandwidth); 763 UINT16_TO_STREAM(pp, max_latency); 764 UINT16_TO_STREAM(pp, content_fmt); 765 UINT8_TO_STREAM(pp, retrans_effort); 766 UINT16_TO_STREAM(pp, packet_types); 767 768 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 769 } 770 771 void btsnd_hcic_reject_esco_conn(const RawAddress& bd_addr, uint8_t reason) { 772 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 773 uint8_t* pp = (uint8_t*)(p + 1); 774 775 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REJECT_ESCO; 776 p->offset = 0; 777 778 UINT16_TO_STREAM(pp, HCI_REJECT_ESCO_CONNECTION); 779 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REJECT_ESCO); 780 781 BDADDR_TO_STREAM(pp, bd_addr); 782 UINT8_TO_STREAM(pp, reason); 783 784 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 785 } 786 787 void btsnd_hcic_hold_mode(uint16_t handle, uint16_t max_hold_period, 788 uint16_t min_hold_period) { 789 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 790 uint8_t* pp = (uint8_t*)(p + 1); 791 792 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_HOLD_MODE; 793 p->offset = 0; 794 795 UINT16_TO_STREAM(pp, HCI_HOLD_MODE); 796 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_HOLD_MODE); 797 798 UINT16_TO_STREAM(pp, handle); 799 UINT16_TO_STREAM(pp, max_hold_period); 800 UINT16_TO_STREAM(pp, min_hold_period); 801 802 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 803 } 804 805 void btsnd_hcic_sniff_mode(uint16_t handle, uint16_t max_sniff_period, 806 uint16_t min_sniff_period, uint16_t sniff_attempt, 807 uint16_t sniff_timeout) { 808 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 809 uint8_t* pp = (uint8_t*)(p + 1); 810 811 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_MODE; 812 p->offset = 0; 813 814 UINT16_TO_STREAM(pp, HCI_SNIFF_MODE); 815 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_MODE); 816 817 UINT16_TO_STREAM(pp, handle); 818 UINT16_TO_STREAM(pp, max_sniff_period); 819 UINT16_TO_STREAM(pp, min_sniff_period); 820 UINT16_TO_STREAM(pp, sniff_attempt); 821 UINT16_TO_STREAM(pp, sniff_timeout); 822 823 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 824 } 825 826 void btsnd_hcic_exit_sniff_mode(uint16_t handle) { 827 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 828 uint8_t* pp = (uint8_t*)(p + 1); 829 830 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 831 p->offset = 0; 832 833 UINT16_TO_STREAM(pp, HCI_EXIT_SNIFF_MODE); 834 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 835 836 UINT16_TO_STREAM(pp, handle); 837 838 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 839 } 840 841 void btsnd_hcic_park_mode(uint16_t handle, uint16_t beacon_max_interval, 842 uint16_t beacon_min_interval) { 843 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 844 uint8_t* pp = (uint8_t*)(p + 1); 845 846 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_PARK_MODE; 847 p->offset = 0; 848 849 UINT16_TO_STREAM(pp, HCI_PARK_MODE); 850 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_PARK_MODE); 851 852 UINT16_TO_STREAM(pp, handle); 853 UINT16_TO_STREAM(pp, beacon_max_interval); 854 UINT16_TO_STREAM(pp, beacon_min_interval); 855 856 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 857 } 858 859 void btsnd_hcic_exit_park_mode(uint16_t handle) { 860 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 861 uint8_t* pp = (uint8_t*)(p + 1); 862 863 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 864 p->offset = 0; 865 866 UINT16_TO_STREAM(pp, HCI_EXIT_PARK_MODE); 867 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 868 869 UINT16_TO_STREAM(pp, handle); 870 871 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 872 } 873 874 static void btsnd_hcic_switch_role(const RawAddress& bd_addr, uint8_t role) { 875 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 876 uint8_t* pp = (uint8_t*)(p + 1); 877 878 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SWITCH_ROLE; 879 p->offset = 0; 880 881 UINT16_TO_STREAM(pp, HCI_SWITCH_ROLE); 882 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SWITCH_ROLE); 883 884 BDADDR_TO_STREAM(pp, bd_addr); 885 UINT8_TO_STREAM(pp, role); 886 887 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 888 } 889 890 void btsnd_hcic_write_policy_set(uint16_t handle, uint16_t settings) { 891 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 892 uint8_t* pp = (uint8_t*)(p + 1); 893 894 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_POLICY_SET; 895 p->offset = 0; 896 UINT16_TO_STREAM(pp, HCI_WRITE_POLICY_SETTINGS); 897 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_POLICY_SET); 898 899 UINT16_TO_STREAM(pp, handle); 900 UINT16_TO_STREAM(pp, settings); 901 902 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 903 } 904 905 void btsnd_hcic_write_def_policy_set(uint16_t settings) { 906 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 907 uint8_t* pp = (uint8_t*)(p + 1); 908 909 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET; 910 p->offset = 0; 911 UINT16_TO_STREAM(pp, HCI_WRITE_DEF_POLICY_SETTINGS); 912 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_DEF_POLICY_SET); 913 914 UINT16_TO_STREAM(pp, settings); 915 916 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 917 } 918 919 void btsnd_hcic_set_event_filter(uint8_t filt_type, uint8_t filt_cond_type, 920 uint8_t* filt_cond, uint8_t filt_cond_len) { 921 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 922 uint8_t* pp = (uint8_t*)(p + 1); 923 924 p->offset = 0; 925 926 UINT16_TO_STREAM(pp, HCI_SET_EVENT_FILTER); 927 928 if (filt_type) { 929 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 2 + filt_cond_len); 930 UINT8_TO_STREAM(pp, (uint8_t)(2 + filt_cond_len)); 931 932 UINT8_TO_STREAM(pp, filt_type); 933 UINT8_TO_STREAM(pp, filt_cond_type); 934 935 if (filt_cond_type == HCI_FILTER_COND_DEVICE_CLASS) { 936 DEVCLASS_TO_STREAM(pp, filt_cond); 937 filt_cond += kDevClassLength; 938 DEVCLASS_TO_STREAM(pp, filt_cond); 939 filt_cond += kDevClassLength; 940 941 filt_cond_len -= (2 * kDevClassLength); 942 } else if (filt_cond_type == HCI_FILTER_COND_BD_ADDR) { 943 BDADDR_TO_STREAM(pp, *((RawAddress*)filt_cond)); 944 filt_cond += BD_ADDR_LEN; 945 946 filt_cond_len -= BD_ADDR_LEN; 947 } 948 949 if (filt_cond_len) ARRAY_TO_STREAM(pp, filt_cond, filt_cond_len); 950 } else { 951 p->len = (uint16_t)(HCIC_PREAMBLE_SIZE + 1); 952 UINT8_TO_STREAM(pp, 1); 953 954 UINT8_TO_STREAM(pp, filt_type); 955 } 956 957 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 958 } 959 960 void btsnd_hcic_write_pin_type(uint8_t type) { 961 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 962 uint8_t* pp = (uint8_t*)(p + 1); 963 964 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 965 p->offset = 0; 966 967 UINT16_TO_STREAM(pp, HCI_WRITE_PIN_TYPE); 968 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 969 970 UINT8_TO_STREAM(pp, type); 971 972 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 973 } 974 975 void btsnd_hcic_delete_stored_key(const RawAddress& bd_addr, 976 bool delete_all_flag) { 977 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 978 uint8_t* pp = (uint8_t*)(p + 1); 979 980 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_DELETE_STORED_KEY; 981 p->offset = 0; 982 983 UINT16_TO_STREAM(pp, HCI_DELETE_STORED_LINK_KEY); 984 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_DELETE_STORED_KEY); 985 986 BDADDR_TO_STREAM(pp, bd_addr); 987 UINT8_TO_STREAM(pp, delete_all_flag); 988 989 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 990 } 991 992 void btsnd_hcic_change_name(BD_NAME name) { 993 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 994 uint8_t* pp = (uint8_t*)(p + 1); 995 uint16_t len = strlen((char*)name) + 1; 996 997 memset(pp, 0, HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME); 998 999 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CHANGE_NAME; 1000 p->offset = 0; 1001 1002 UINT16_TO_STREAM(pp, HCI_CHANGE_LOCAL_NAME); 1003 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CHANGE_NAME); 1004 1005 if (len > HCIC_PARAM_SIZE_CHANGE_NAME) len = HCIC_PARAM_SIZE_CHANGE_NAME; 1006 1007 ARRAY_TO_STREAM(pp, name, len); 1008 1009 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1010 } 1011 1012 void btsnd_hcic_read_name(void) { 1013 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1014 uint8_t* pp = (uint8_t*)(p + 1); 1015 1016 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 1017 p->offset = 0; 1018 1019 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_NAME); 1020 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD); 1021 1022 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1023 } 1024 1025 void btsnd_hcic_write_page_tout(uint16_t timeout) { 1026 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1027 uint8_t* pp = (uint8_t*)(p + 1); 1028 1029 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 1030 p->offset = 0; 1031 1032 UINT16_TO_STREAM(pp, HCI_WRITE_PAGE_TOUT); 1033 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 1034 1035 UINT16_TO_STREAM(pp, timeout); 1036 1037 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1038 } 1039 1040 void btsnd_hcic_write_scan_enable(uint8_t flag) { 1041 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1042 uint8_t* pp = (uint8_t*)(p + 1); 1043 1044 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1045 p->offset = 0; 1046 1047 UINT16_TO_STREAM(pp, HCI_WRITE_SCAN_ENABLE); 1048 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1049 1050 UINT8_TO_STREAM(pp, flag); 1051 1052 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1053 } 1054 1055 void btsnd_hcic_write_pagescan_cfg(uint16_t interval, uint16_t window) { 1056 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1057 uint8_t* pp = (uint8_t*)(p + 1); 1058 1059 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG; 1060 p->offset = 0; 1061 1062 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_CFG); 1063 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PAGESCAN_CFG); 1064 1065 UINT16_TO_STREAM(pp, interval); 1066 UINT16_TO_STREAM(pp, window); 1067 1068 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1069 } 1070 1071 void btsnd_hcic_write_inqscan_cfg(uint16_t interval, uint16_t window) { 1072 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1073 uint8_t* pp = (uint8_t*)(p + 1); 1074 1075 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG; 1076 p->offset = 0; 1077 1078 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRYSCAN_CFG); 1079 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_INQSCAN_CFG); 1080 1081 UINT16_TO_STREAM(pp, interval); 1082 UINT16_TO_STREAM(pp, window); 1083 1084 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1085 } 1086 1087 void btsnd_hcic_write_auth_enable(uint8_t flag) { 1088 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1089 uint8_t* pp = (uint8_t*)(p + 1); 1090 1091 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1092 p->offset = 0; 1093 1094 UINT16_TO_STREAM(pp, HCI_WRITE_AUTHENTICATION_ENABLE); 1095 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1096 1097 UINT8_TO_STREAM(pp, flag); 1098 1099 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1100 } 1101 1102 void btsnd_hcic_write_dev_class(DEV_CLASS dev_class) { 1103 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1104 uint8_t* pp = (uint8_t*)(p + 1); 1105 1106 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM3; 1107 p->offset = 0; 1108 1109 UINT16_TO_STREAM(pp, HCI_WRITE_CLASS_OF_DEVICE); 1110 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM3); 1111 1112 DEVCLASS_TO_STREAM(pp, dev_class); 1113 1114 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1115 } 1116 1117 void btsnd_hcic_write_voice_settings(uint16_t flags) { 1118 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1119 uint8_t* pp = (uint8_t*)(p + 1); 1120 1121 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM2; 1122 p->offset = 0; 1123 1124 UINT16_TO_STREAM(pp, HCI_WRITE_VOICE_SETTINGS); 1125 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM2); 1126 1127 UINT16_TO_STREAM(pp, flags); 1128 1129 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1130 } 1131 1132 void btsnd_hcic_write_auto_flush_tout(uint16_t handle, uint16_t tout) { 1133 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1134 uint8_t* pp = (uint8_t*)(p + 1); 1135 1136 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT; 1137 p->offset = 0; 1138 1139 UINT16_TO_STREAM(pp, HCI_WRITE_AUTOMATIC_FLUSH_TIMEOUT); 1140 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_AUTOMATIC_FLUSH_TIMEOUT); 1141 1142 UINT16_TO_STREAM(pp, handle); 1143 UINT16_TO_STREAM(pp, tout); 1144 1145 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1146 } 1147 1148 void btsnd_hcic_read_tx_power(uint16_t handle, uint8_t type) { 1149 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1150 uint8_t* pp = (uint8_t*)(p + 1); 1151 1152 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_TX_POWER; 1153 p->offset = 0; 1154 1155 UINT16_TO_STREAM(pp, HCI_READ_TRANSMIT_POWER_LEVEL); 1156 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_TX_POWER); 1157 1158 UINT16_TO_STREAM(pp, handle); 1159 UINT8_TO_STREAM(pp, type); 1160 1161 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1162 } 1163 1164 void btsnd_hcic_write_link_super_tout(uint16_t handle, uint16_t timeout) { 1165 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1166 uint8_t* pp = (uint8_t*)(p + 1); 1167 1168 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT; 1169 p->offset = 0; 1170 1171 UINT16_TO_STREAM(pp, HCI_WRITE_LINK_SUPER_TOUT); 1172 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_LINK_SUPER_TOUT); 1173 1174 UINT16_TO_STREAM(pp, handle); 1175 UINT16_TO_STREAM(pp, timeout); 1176 1177 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1178 } 1179 1180 void btsnd_hcic_write_cur_iac_lap(uint8_t num_cur_iac, LAP* const iac_lap) { 1181 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1182 uint8_t* pp = (uint8_t*)(p + 1); 1183 1184 p->len = HCIC_PREAMBLE_SIZE + 1 + (LAP_LEN * num_cur_iac); 1185 p->offset = 0; 1186 1187 UINT16_TO_STREAM(pp, HCI_WRITE_CURRENT_IAC_LAP); 1188 UINT8_TO_STREAM(pp, p->len - HCIC_PREAMBLE_SIZE); 1189 1190 UINT8_TO_STREAM(pp, num_cur_iac); 1191 1192 for (int i = 0; i < num_cur_iac; i++) LAP_TO_STREAM(pp, iac_lap[i]); 1193 1194 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1195 } 1196 1197 /****************************************** 1198 * Lisbon Features 1199 ******************************************/ 1200 void btsnd_hcic_sniff_sub_rate(uint16_t handle, uint16_t max_lat, 1201 uint16_t min_remote_lat, 1202 uint16_t min_local_lat) { 1203 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1204 uint8_t* pp = (uint8_t*)(p + 1); 1205 1206 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_SNIFF_SUB_RATE; 1207 p->offset = 0; 1208 1209 UINT16_TO_STREAM(pp, HCI_SNIFF_SUB_RATE); 1210 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_SNIFF_SUB_RATE); 1211 1212 UINT16_TO_STREAM(pp, handle); 1213 UINT16_TO_STREAM(pp, max_lat); 1214 UINT16_TO_STREAM(pp, min_remote_lat); 1215 UINT16_TO_STREAM(pp, min_local_lat); 1216 1217 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1218 } 1219 1220 /**** Extended Inquiry Response Commands ****/ 1221 void btsnd_hcic_write_ext_inquiry_response(void* buffer, uint8_t fec_req) { 1222 BT_HDR* p = (BT_HDR*)buffer; 1223 uint8_t* pp = (uint8_t*)(p + 1); 1224 1225 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_EXT_INQ_RESP; 1226 p->offset = 0; 1227 1228 UINT16_TO_STREAM(pp, HCI_WRITE_EXT_INQ_RESPONSE); 1229 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_EXT_INQ_RESP); 1230 1231 UINT8_TO_STREAM(pp, fec_req); 1232 1233 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1234 } 1235 1236 void btsnd_hcic_io_cap_req_reply(const RawAddress& bd_addr, uint8_t capability, 1237 uint8_t oob_present, uint8_t auth_req) { 1238 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1239 uint8_t* pp = (uint8_t*)(p + 1); 1240 1241 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_RESP; 1242 p->offset = 0; 1243 1244 UINT16_TO_STREAM(pp, HCI_IO_CAPABILITY_REQUEST_REPLY); 1245 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_RESP); 1246 1247 BDADDR_TO_STREAM(pp, bd_addr); 1248 UINT8_TO_STREAM(pp, capability); 1249 UINT8_TO_STREAM(pp, oob_present); 1250 UINT8_TO_STREAM(pp, auth_req); 1251 1252 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1253 } 1254 1255 void btsnd_hcic_enhanced_set_up_synchronous_connection( 1256 uint16_t conn_handle, enh_esco_params_t* p_params) { 1257 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1258 uint8_t* pp = (uint8_t*)(p + 1); 1259 1260 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN; 1261 p->offset = 0; 1262 1263 UINT16_TO_STREAM(pp, HCI_ENH_SETUP_ESCO_CONNECTION); 1264 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_SET_ESCO_CONN); 1265 1266 UINT16_TO_STREAM(pp, conn_handle); 1267 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth); 1268 UINT32_TO_STREAM(pp, p_params->receive_bandwidth); 1269 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format); 1270 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id); 1271 UINT16_TO_STREAM(pp, 1272 p_params->transmit_coding_format.vendor_specific_codec_id); 1273 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format); 1274 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id); 1275 UINT16_TO_STREAM(pp, 1276 p_params->receive_coding_format.vendor_specific_codec_id); 1277 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size); 1278 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size); 1279 UINT32_TO_STREAM(pp, p_params->input_bandwidth); 1280 UINT32_TO_STREAM(pp, p_params->output_bandwidth); 1281 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format); 1282 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id); 1283 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id); 1284 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format); 1285 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id); 1286 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id); 1287 UINT16_TO_STREAM(pp, p_params->input_coded_data_size); 1288 UINT16_TO_STREAM(pp, p_params->output_coded_data_size); 1289 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format); 1290 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format); 1291 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position); 1292 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position); 1293 UINT8_TO_STREAM(pp, p_params->input_data_path); 1294 UINT8_TO_STREAM(pp, p_params->output_data_path); 1295 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size); 1296 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size); 1297 UINT16_TO_STREAM(pp, p_params->max_latency_ms); 1298 UINT16_TO_STREAM(pp, p_params->packet_types); 1299 UINT8_TO_STREAM(pp, p_params->retransmission_effort); 1300 1301 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1302 } 1303 1304 void btsnd_hcic_enhanced_accept_synchronous_connection( 1305 const RawAddress& bd_addr, enh_esco_params_t* p_params) { 1306 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1307 uint8_t* pp = (uint8_t*)(p + 1); 1308 1309 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN; 1310 p->offset = 0; 1311 1312 UINT16_TO_STREAM(pp, HCI_ENH_ACCEPT_ESCO_CONNECTION); 1313 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_ENH_ACC_ESCO_CONN); 1314 1315 BDADDR_TO_STREAM(pp, bd_addr); 1316 UINT32_TO_STREAM(pp, p_params->transmit_bandwidth); 1317 UINT32_TO_STREAM(pp, p_params->receive_bandwidth); 1318 UINT8_TO_STREAM(pp, p_params->transmit_coding_format.coding_format); 1319 UINT16_TO_STREAM(pp, p_params->transmit_coding_format.company_id); 1320 UINT16_TO_STREAM(pp, 1321 p_params->transmit_coding_format.vendor_specific_codec_id); 1322 UINT8_TO_STREAM(pp, p_params->receive_coding_format.coding_format); 1323 UINT16_TO_STREAM(pp, p_params->receive_coding_format.company_id); 1324 UINT16_TO_STREAM(pp, 1325 p_params->receive_coding_format.vendor_specific_codec_id); 1326 UINT16_TO_STREAM(pp, p_params->transmit_codec_frame_size); 1327 UINT16_TO_STREAM(pp, p_params->receive_codec_frame_size); 1328 UINT32_TO_STREAM(pp, p_params->input_bandwidth); 1329 UINT32_TO_STREAM(pp, p_params->output_bandwidth); 1330 UINT8_TO_STREAM(pp, p_params->input_coding_format.coding_format); 1331 UINT16_TO_STREAM(pp, p_params->input_coding_format.company_id); 1332 UINT16_TO_STREAM(pp, p_params->input_coding_format.vendor_specific_codec_id); 1333 UINT8_TO_STREAM(pp, p_params->output_coding_format.coding_format); 1334 UINT16_TO_STREAM(pp, p_params->output_coding_format.company_id); 1335 UINT16_TO_STREAM(pp, p_params->output_coding_format.vendor_specific_codec_id); 1336 UINT16_TO_STREAM(pp, p_params->input_coded_data_size); 1337 UINT16_TO_STREAM(pp, p_params->output_coded_data_size); 1338 UINT8_TO_STREAM(pp, p_params->input_pcm_data_format); 1339 UINT8_TO_STREAM(pp, p_params->output_pcm_data_format); 1340 UINT8_TO_STREAM(pp, p_params->input_pcm_payload_msb_position); 1341 UINT8_TO_STREAM(pp, p_params->output_pcm_payload_msb_position); 1342 UINT8_TO_STREAM(pp, p_params->input_data_path); 1343 UINT8_TO_STREAM(pp, p_params->output_data_path); 1344 UINT8_TO_STREAM(pp, p_params->input_transport_unit_size); 1345 UINT8_TO_STREAM(pp, p_params->output_transport_unit_size); 1346 UINT16_TO_STREAM(pp, p_params->max_latency_ms); 1347 UINT16_TO_STREAM(pp, p_params->packet_types); 1348 UINT8_TO_STREAM(pp, p_params->retransmission_effort); 1349 1350 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1351 } 1352 1353 void btsnd_hcic_io_cap_req_neg_reply(const RawAddress& bd_addr, 1354 uint8_t err_code) { 1355 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1356 uint8_t* pp = (uint8_t*)(p + 1); 1357 1358 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY; 1359 p->offset = 0; 1360 1361 UINT16_TO_STREAM(pp, HCI_IO_CAP_REQ_NEG_REPLY); 1362 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_IO_CAP_NEG_REPLY); 1363 1364 BDADDR_TO_STREAM(pp, bd_addr); 1365 UINT8_TO_STREAM(pp, err_code); 1366 1367 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1368 } 1369 1370 void btsnd_hcic_read_local_oob_data(void) { 1371 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1372 uint8_t* pp = (uint8_t*)(p + 1); 1373 1374 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB; 1375 p->offset = 0; 1376 1377 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_DATA); 1378 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB); 1379 1380 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1381 } 1382 1383 void btsnd_hcic_read_local_oob_extended_data(void) { 1384 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1385 uint8_t* pp = (uint8_t*)(p + 1); 1386 1387 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED; 1388 p->offset = 0; 1389 1390 UINT16_TO_STREAM(pp, HCI_READ_LOCAL_OOB_EXTENDED_DATA); 1391 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_R_LOCAL_OOB_EXTENDED); 1392 1393 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1394 } 1395 1396 void btsnd_hcic_user_conf_reply(const RawAddress& bd_addr, bool is_yes) { 1397 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1398 uint8_t* pp = (uint8_t*)(p + 1); 1399 1400 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_UCONF_REPLY; 1401 p->offset = 0; 1402 1403 if (!is_yes) { 1404 /* Negative reply */ 1405 UINT16_TO_STREAM(pp, HCI_USER_CONF_VALUE_NEG_REPLY); 1406 } else { 1407 /* Confirmation */ 1408 UINT16_TO_STREAM(pp, HCI_USER_CONF_REQUEST_REPLY); 1409 } 1410 1411 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_UCONF_REPLY); 1412 1413 BDADDR_TO_STREAM(pp, bd_addr); 1414 1415 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1416 } 1417 1418 void btsnd_hcic_user_passkey_reply(const RawAddress& bd_addr, uint32_t value) { 1419 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1420 uint8_t* pp = (uint8_t*)(p + 1); 1421 1422 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_REPLY; 1423 p->offset = 0; 1424 1425 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_REPLY); 1426 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_REPLY); 1427 1428 BDADDR_TO_STREAM(pp, bd_addr); 1429 UINT32_TO_STREAM(pp, value); 1430 1431 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1432 } 1433 1434 void btsnd_hcic_user_passkey_neg_reply(const RawAddress& bd_addr) { 1435 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1436 uint8_t* pp = (uint8_t*)(p + 1); 1437 1438 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY; 1439 p->offset = 0; 1440 1441 UINT16_TO_STREAM(pp, HCI_USER_PASSKEY_REQ_NEG_REPLY); 1442 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_U_PKEY_NEG_REPLY); 1443 1444 BDADDR_TO_STREAM(pp, bd_addr); 1445 1446 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1447 } 1448 1449 void btsnd_hcic_rem_oob_reply(const RawAddress& bd_addr, const Octet16& c, 1450 const Octet16& r) { 1451 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1452 uint8_t* pp = (uint8_t*)(p + 1); 1453 1454 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_REPLY; 1455 p->offset = 0; 1456 1457 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_REPLY); 1458 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_REPLY); 1459 1460 BDADDR_TO_STREAM(pp, bd_addr); 1461 ARRAY16_TO_STREAM(pp, c.data()); 1462 ARRAY16_TO_STREAM(pp, r.data()); 1463 1464 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1465 } 1466 1467 void btsnd_hcic_rem_oob_neg_reply(const RawAddress& bd_addr) { 1468 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1469 uint8_t* pp = (uint8_t*)(p + 1); 1470 1471 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY; 1472 p->offset = 0; 1473 1474 UINT16_TO_STREAM(pp, HCI_REM_OOB_DATA_REQ_NEG_REPLY); 1475 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_REM_OOB_NEG_REPLY); 1476 1477 BDADDR_TO_STREAM(pp, bd_addr); 1478 1479 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1480 } 1481 1482 /**** end of Simple Pairing Commands ****/ 1483 1484 /************************* 1485 * End of Lisbon Commands 1486 *************************/ 1487 1488 void btsnd_hcic_read_rssi(uint16_t handle) { 1489 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1490 uint8_t* pp = (uint8_t*)(p + 1); 1491 1492 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1493 p->offset = 0; 1494 1495 UINT16_TO_STREAM(pp, HCI_READ_RSSI); 1496 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1497 1498 UINT16_TO_STREAM(pp, handle); 1499 1500 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1501 } 1502 1503 static void read_encryption_key_size_complete( 1504 ReadEncKeySizeCb cb, uint8_t* return_parameters, 1505 uint16_t /* return_parameters_length */) { 1506 uint8_t status; 1507 uint16_t handle; 1508 uint8_t key_size; 1509 STREAM_TO_UINT8(status, return_parameters); 1510 STREAM_TO_UINT16(handle, return_parameters); 1511 STREAM_TO_UINT8(key_size, return_parameters); 1512 1513 std::move(cb).Run(status, handle, key_size); 1514 } 1515 1516 void btsnd_hcic_read_encryption_key_size(uint16_t handle, ReadEncKeySizeCb cb) { 1517 constexpr uint8_t len = 2; 1518 uint8_t param[len]; 1519 memset(param, 0, len); 1520 1521 uint8_t* p = param; 1522 UINT16_TO_STREAM(p, handle); 1523 1524 btu_hcif_send_cmd_with_cb(FROM_HERE, HCI_READ_ENCR_KEY_SIZE, param, len, 1525 base::Bind(&read_encryption_key_size_complete, base::Passed(&cb))); 1526 } 1527 1528 void btsnd_hcic_read_failed_contact_counter(uint16_t handle) { 1529 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1530 uint8_t* pp = (uint8_t*)(p + 1); 1531 1532 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CMD_HANDLE; 1533 p->offset = 0; 1534 1535 UINT16_TO_STREAM(pp, HCI_READ_FAILED_CONTACT_COUNTER); 1536 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CMD_HANDLE); 1537 1538 UINT16_TO_STREAM(pp, handle); 1539 1540 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1541 } 1542 1543 void btsnd_hcic_enable_test_mode(void) { 1544 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1545 uint8_t* pp = (uint8_t*)(p + 1); 1546 1547 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_READ_CMD; 1548 p->offset = 0; 1549 1550 UINT16_TO_STREAM(pp, HCI_ENABLE_DEV_UNDER_TEST_MODE); 1551 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_READ_CMD); 1552 1553 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1554 } 1555 1556 void btsnd_hcic_write_inqscan_type(uint8_t type) { 1557 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1558 uint8_t* pp = (uint8_t*)(p + 1); 1559 1560 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1561 p->offset = 0; 1562 1563 UINT16_TO_STREAM(pp, HCI_WRITE_INQSCAN_TYPE); 1564 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1565 1566 UINT8_TO_STREAM(pp, type); 1567 1568 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1569 } 1570 1571 void btsnd_hcic_write_inquiry_mode(uint8_t mode) { 1572 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1573 uint8_t* pp = (uint8_t*)(p + 1); 1574 1575 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1576 p->offset = 0; 1577 1578 UINT16_TO_STREAM(pp, HCI_WRITE_INQUIRY_MODE); 1579 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1580 1581 UINT8_TO_STREAM(pp, mode); 1582 1583 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1584 } 1585 1586 void btsnd_hcic_write_pagescan_type(uint8_t type) { 1587 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1588 uint8_t* pp = (uint8_t*)(p + 1); 1589 1590 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_WRITE_PARAM1; 1591 p->offset = 0; 1592 1593 UINT16_TO_STREAM(pp, HCI_WRITE_PAGESCAN_TYPE); 1594 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_WRITE_PARAM1); 1595 1596 UINT8_TO_STREAM(pp, type); 1597 1598 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1599 } 1600 1601 static void btsnd_hcic_vendor_spec_complete(tBTM_VSC_CMPL_CB* p_vsc_cplt_cback, 1602 uint16_t opcode, uint8_t* data, 1603 uint16_t len) { 1604 /* If there was a callback address for vcs complete, call it */ 1605 if (p_vsc_cplt_cback) { 1606 tBTM_VSC_CMPL vcs_cplt_params; 1607 vcs_cplt_params.opcode = opcode; 1608 vcs_cplt_params.param_len = len; 1609 vcs_cplt_params.p_param_buf = data; 1610 /* Call the VSC complete callback function */ 1611 (*p_vsc_cplt_cback)(&vcs_cplt_params); 1612 } 1613 } 1614 1615 void btsnd_hcic_vendor_spec_cmd(uint16_t opcode, uint8_t len, uint8_t* p_data, 1616 tBTM_VSC_CMPL_CB* p_cmd_cplt_cback) { 1617 uint16_t v_opcode = HCI_GRP_VENDOR_SPECIFIC | opcode; 1618 1619 btu_hcif_send_cmd_with_cb( 1620 FROM_HERE, v_opcode, p_data, len, 1621 base::BindOnce(&btsnd_hcic_vendor_spec_complete, 1622 base::Unretained(p_cmd_cplt_cback), v_opcode)); 1623 } 1624 1625 void btsnd_hcic_configure_data_path(hci_data_direction_t data_path_direction, 1626 uint8_t data_path_id, 1627 std::vector<uint8_t> vendor_config) { 1628 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1629 uint8_t* pp = (uint8_t*)(p + 1); 1630 uint8_t size = static_cast<uint8_t>(vendor_config.size()); 1631 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size; 1632 p->offset = 0; 1633 1634 UINT16_TO_STREAM(pp, HCI_CONFIGURE_DATA_PATH); 1635 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_CONFIGURE_DATA_PATH + size); 1636 UINT8_TO_STREAM(pp, data_path_direction); 1637 UINT8_TO_STREAM(pp, data_path_id); 1638 UINT8_TO_STREAM(pp, vendor_config.size()); 1639 if (size != 0) { 1640 ARRAY_TO_STREAM(pp, vendor_config.data(), size); 1641 } 1642 1643 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1644 } 1645 1646 namespace bluetooth::legacy::hci { 1647 class InterfaceImpl : public Interface { 1648 void Disconnect(uint16_t handle, uint8_t reason) const override { 1649 btsnd_hcic_disconnect(handle, reason); 1650 } 1651 void ChangeConnectionPacketType(uint16_t handle, 1652 uint16_t packet_types) const override { 1653 btsnd_hcic_change_conn_type(handle, packet_types); 1654 } 1655 void StartRoleSwitch(const RawAddress& bd_addr, uint8_t role) const override { 1656 btsnd_hcic_switch_role(bd_addr, role); 1657 } 1658 void ConfigureDataPath(hci_data_direction_t data_path_direction, 1659 uint8_t data_path_id, 1660 std::vector<uint8_t> vendor_config) const override { 1661 btsnd_hcic_configure_data_path(data_path_direction, data_path_id, 1662 vendor_config); 1663 } 1664 void SendVendorSpecificCmd(unsigned short opcode, 1665 unsigned char len, unsigned char* param, void (*cb)(tBTM_VSC_CMPL*)) const override { 1666 btsnd_hcic_vendor_spec_cmd(opcode, len, param, cb); 1667 } 1668 }; 1669 1670 namespace { 1671 const InterfaceImpl interface_; 1672 } 1673 1674 const Interface& GetInterface() { return interface_; } 1675 } // namespace bluetooth::legacy::hci 1676 1677 void btsnd_hcic_flow_spec(uint16_t handle, uint8_t unused, uint8_t direction, 1678 uint8_t service_type, uint32_t token_rate, 1679 uint32_t token_size, uint32_t peak, uint32_t latency){ 1680 1681 BT_HDR* p = (BT_HDR*)osi_malloc(HCI_CMD_BUF_SIZE); 1682 uint8_t* pp = (uint8_t*)(p + 1); 1683 1684 p->len = HCIC_PREAMBLE_SIZE + HCIC_PARAM_SIZE_FLOW_SPECIFICATION; 1685 p->offset = 0; 1686 1687 UINT16_TO_STREAM(pp, HCI_FLOW_SPECIFICATION); 1688 UINT8_TO_STREAM(pp, HCIC_PARAM_SIZE_FLOW_SPECIFICATION); 1689 1690 UINT16_TO_STREAM(pp, handle); 1691 UINT8_TO_STREAM(pp, unused); 1692 UINT8_TO_STREAM(pp, direction); 1693 UINT8_TO_STREAM(pp, service_type); 1694 UINT32_TO_STREAM(pp, token_rate); 1695 UINT32_TO_STREAM(pp, token_size); 1696 UINT32_TO_STREAM(pp, peak); 1697 UINT32_TO_STREAM(pp, latency); 1698 1699 btu_hcif_send_cmd(LOCAL_BR_EDR_CONTROLLER_ID, p); 1700 }
07-18
AnnotateLine# Scopes# Navigate#Raw Download current directory 1 /* 2 * Copyright 2024 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #define LOG_TAG "bt_bta_sd" 18 19 #include "bta/dm/bta_dm_device_search.h" 20 21 #include <base/functional/bind.h> 22 #include <base/strings/stringprintf.h> 23 #include <bluetooth/log.h> 24 #include <com_android_bluetooth_flags.h> 25 #include <stddef.h> 26 27 #include <cstdint> 28 #include <string> 29 #include <variant> 30 #include <vector> 31 32 #include "bta/dm/bta_dm_device_search_int.h" 33 #include "bta/dm/bta_dm_disc_legacy.h" 34 #include "bta/include/bta_gatt_api.h" 35 #include "bta/include/bta_sdp_api.h" 36 #include "btif/include/btif_config.h" 37 #include "com_android_bluetooth_flags.h" 38 #include "common/circular_buffer.h" 39 #include "common/init_flags.h" 40 #include "common/strings.h" 41 #include "device/include/interop.h" 42 #include "internal_include/bt_target.h" 43 #include "main/shim/dumpsys.h" 44 #include "os/logging/log_adapter.h" 45 #include "osi/include/allocator.h" 46 #include "stack/btm/btm_int_types.h" // TimestampedStringCircularBuffer 47 #include "stack/btm/neighbor_inquiry.h" 48 #include "stack/include/bt_dev_class.h" 49 #include "stack/include/bt_name.h" 50 #include "stack/include/bt_uuid16.h" 51 #include "stack/include/btm_client_interface.h" 52 #include "stack/include/btm_inq.h" 53 #include "stack/include/btm_log_history.h" 54 #include "stack/include/btm_sec_api.h" // BTM_IsRemoteNameKnown 55 #include "stack/include/gap_api.h" // GAP_BleReadPeerPrefConnParams 56 #include "stack/include/hidh_api.h" 57 #include "stack/include/main_thread.h" 58 #include "stack/include/sdp_status.h" 59 #include "stack/sdp/sdpint.h" // is_sdp_pbap_pce_disabled 60 #include "storage/config_keys.h" 61 #include "types/raw_address.h" 62 //#ifdef OPLUS_BUG_STABILITY 63 //Wanghuaiyin@Connectivity.BT.Basic.7911775, 2024/09/12 64 //Add for address mask output 65 #include "oplus_bt_util.h" 66 //#endif /* OPLUS_BUG_STABILITY */ 67 68 #ifdef OPLUS_FEATURE_BT_HS_INQUIRY 69 #include "btif/include/btif_dm.h" 70 //lvshengyi@CONNECTIVITY.BT.Basic.Inquiry.1678005, 2021/03/09 71 //add for fast inquiry 72 #include "oplus_bt_stack_scan_manager.h" 73 extern tBTM_CB btm_cb; 74 #endif 75 76 #ifdef OPLUS_FEATURE_BT_HS_SDP 77 //lvshengyi@CONNECTIVITY.BT.Basic.SDP.1710878, 2023/10/15 78 #include "oplus_bt_stack_sdp_manager.h" 79 #endif 80 81 //#ifdef OPLUS_BT_STACK_UNIFY 82 #include "oplus_btif_dm.h" 83 #include "oplus_btif_core.h" 84 //#endif /* OPLUS_BT_STACK_UNIFY */ 85 86 #include "common/include/hardware/oplus_vendor.h" /* OPLUS_BT_STACK_UNIFY */ 87 88 #ifdef OPLUS_FEATURE_BT_HS_INQUIRY 89 //zengqiu@CONNECTIVITY.BT.Basic.fast.inquiry 90 #include "oplus_btif_fast_inquiry.h" 91 #include "main/shim/le_scanning_manager.h" 92 93 #ifdef OPLUS_FEATURE_BT_LE_AUDIO 94 #include "oplus_bt_interop.h" 95 #include "btm_ble_adv_data_processor.h" 96 #endif /* OPLUS_FEATURE_BT_LE_AUDIO */ 97 #endif 98 99 using namespace bluetooth; 100 101 namespace { 102 constexpr char kBtmLogTag[] = "DEV_SEARCH"; 103 104 tBTA_DM_SEARCH_CB bta_dm_search_cb; 105 } // namespace 106 107 //#ifdef OPLUS_BUG_COMPATIBILITY 108 //queleiyu@CONNECTIVITY.BT.7544886, 2024/07/22 109 tBTA_DM_SEARCH_CB* bta_dm_get_search_cb() { 110 return &bta_dm_search_cb; 111 } 112 //#endif /* OPLUS_BUG_COMPATIBILITY */ 113 114 static void bta_dm_inq_results_cb(tBTM_INQ_RESULTS* p_inq, const uint8_t* p_eir, 115 uint16_t eir_len); 116 static void bta_dm_inq_cmpl(); 117 static void bta_dm_inq_cmpl_cb(void* p_result); 118 static void bta_dm_search_cmpl(); 119 static void bta_dm_discover_next_device(void); 120 static void bta_dm_remname_cback(const tBTM_REMOTE_DEV_NAME* p); 121 122 static bool bta_dm_read_remote_device_name(const RawAddress& bd_addr, 123 tBT_TRANSPORT transport); 124 static void bta_dm_discover_name(const RawAddress& remote_bd_addr); 125 static void bta_dm_execute_queued_search_request(); 126 static void bta_dm_search_cancel_notify(); 127 static void bta_dm_disable_search(); 128 129 static void bta_dm_search_sm_execute(tBTA_DM_DEV_SEARCH_EVT event, 130 std::unique_ptr<tBTA_DM_SEARCH_MSG> msg); 131 static void bta_dm_observe_results_cb(tBTM_INQ_RESULTS* p_inq, 132 const uint8_t* p_eir, uint16_t eir_len); 133 static void bta_dm_observe_cmpl_cb(void* p_result); 134 135 static void bta_dm_search_set_state(tBTA_DM_DEVICE_SEARCH_STATE state) { 136 bta_dm_search_cb.search_state = state; 137 } 138 static tBTA_DM_DEVICE_SEARCH_STATE bta_dm_search_get_state() { 139 return bta_dm_search_cb.search_state; 140 } 141 142 static void post_search_evt(tBTA_DM_DEV_SEARCH_EVT event, 143 std::unique_ptr<tBTA_DM_SEARCH_MSG> msg) { 144 if (do_in_main_thread(FROM_HERE, base::BindOnce(&bta_dm_search_sm_execute, 145 event, std::move(msg))) != 146 BT_STATUS_SUCCESS) { 147 log::error("post_search_evt failed"); 148 } 149 } 150 151 void bta_dm_disc_disable_search() { 152 if (!com::android::bluetooth::flags:: 153 separate_service_and_device_discovery()) { 154 log::info("no-op when flag is disabled"); 155 return; 156 } 157 bta_dm_disable_search(); 158 } 159 160 /******************************************************************************* 161 * 162 * Function bta_dm_search_start 163 * 164 * Description Starts an inquiry 165 * 166 * 167 * Returns void 168 * 169 ******************************************************************************/ 170 static void bta_dm_search_start(tBTA_DM_API_SEARCH& search) { 171 #ifdef OPLUS_FEATURE_BT_HS_INQUIRY 172 //zengqiu@CONNECTIVITY.BT.Basic.fast.inquiry 173 if(get_fast_act_interface()->enable_inquiry_optimize()) { 174 bluetooth::shim::initAddressCacheExt(); 175 } 176 #endif 177 178 #ifdef OPLUS_FEATURE_BT_HS_INQUIRY 179 //lvshengyi@CONNECTIVITY.BT.Basic.Inquiry.1653415, 2021/03/09 180 if (btm_cb.btm_inq_vars.inq_num == 0) { 181 get_btm_client_interface().db.BTM_ClearInqDb(nullptr); 182 } 183 #else /* OPLUS_FEATURE_BT_HS_INQUIRY */ 184 if (get_btm_client_interface().db.BTM_ClearInqDb(nullptr) != BTM_SUCCESS) { 185 log::warn("Unable to clear inquiry database for device discovery"); 186 } 187 #endif/*OPLUS_FEATURE_BT_HS_INQUIRY*/ 188 /* save search params */ 189 bta_dm_search_cb.p_device_search_cback = search.p_cback; 190 191 const tBTM_STATUS btm_status = 192 BTM_StartInquiry(bta_dm_inq_results_cb, bta_dm_inq_cmpl_cb); 193 switch (btm_status) { 194 case BTM_CMD_STARTED: 195 // Completion callback will be executed when controller inquiry 196 // timer pops or is cancelled by the user 197 break; 198 default: 199 log::warn("Unable to start device discovery search btm_status:{}", 200 btm_status_text(btm_status)); 201 // Not started so completion callback is executed now 202 bta_dm_inq_cmpl(); 203 break; 204 } 205 } 206 207 /******************************************************************************* 208 * 209 * Function bta_dm_search_cancel 210 * 211 * Description Cancels an ongoing search for devices 212 * 213 * 214 * Returns void 215 * 216 ******************************************************************************/ 217 static void bta_dm_search_cancel() { 218 if (BTM_IsInquiryActive()) { 219 BTM_CancelInquiry(); 220 bta_dm_search_cancel_notify(); 221 bta_dm_search_cmpl(); 222 } 223 /* If no Service Search going on then issue cancel remote name in case it is 224 active */ 225 else if (!bta_dm_search_cb.name_discover_done) { 226 if (get_btm_client_interface().peer.BTM_CancelRemoteDeviceName() != 227 BTM_CMD_STARTED) { 228 log::warn("Unable to cancel RNR"); 229 } 230 /* bta_dm_search_cmpl is called when receiving the remote name cancel evt */ 231 if (!com::android::bluetooth::flags:: 232 bta_dm_defer_device_discovery_state_change_until_rnr_complete()) { 233 bta_dm_search_cmpl(); 234 } 235 } else { 236 bta_dm_inq_cmpl(); 237 } 238 } 239 240 /******************************************************************************* 241 * 242 * Function bta_dm_inq_cmpl_cb 243 * 244 * Description Inquiry complete callback from BTM 245 * 246 * Returns void 247 * 248 ******************************************************************************/ 249 static void bta_dm_inq_cmpl_cb(void* /* p_result */) { 250 log::verbose(""); 251 252 bta_dm_inq_cmpl(); 253 } 254 255 /******************************************************************************* 256 * 257 * Function bta_dm_inq_results_cb 258 * 259 * Description Inquiry results callback from BTM 260 * 261 * Returns void 262 * 263 ******************************************************************************/ 264 static void bta_dm_inq_results_cb(tBTM_INQ_RESULTS* p_inq, const uint8_t* p_eir, 265 uint16_t eir_len) { 266 tBTA_DM_SEARCH result; 267 tBTM_INQ_INFO* p_inq_info; 268 uint16_t service_class; 269 270 result.inq_res.bd_addr = p_inq->remote_bd_addr; 271 272 // Pass the original address to GattService#onScanResult 273 result.inq_res.original_bda = p_inq->original_bda; 274 275 result.inq_res.dev_class = p_inq->dev_class; 276 BTM_COD_SERVICE_CLASS(service_class, p_inq->dev_class); 277 result.inq_res.is_limited = 278 (service_class & BTM_COD_SERVICE_LMTD_DISCOVER) ? true : false; 279 result.inq_res.rssi = p_inq->rssi; 280 281 result.inq_res.ble_addr_type = p_inq->ble_addr_type; 282 result.inq_res.inq_result_type = p_inq->inq_result_type; 283 result.inq_res.device_type = p_inq->device_type; 284 result.inq_res.flag = p_inq->flag; 285 result.inq_res.include_rsi = p_inq->include_rsi; 286 result.inq_res.clock_offset = p_inq->clock_offset; 287 288 /* application will parse EIR to find out remote device name */ 289 result.inq_res.p_eir = const_cast<uint8_t*>(p_eir); 290 result.inq_res.eir_len = eir_len; 291 292 result.inq_res.ble_evt_type = p_inq->ble_evt_type; 293 294 p_inq_info = 295 get_btm_client_interface().db.BTM_InqDbRead(p_inq->remote_bd_addr); 296 if (p_inq_info != NULL) { 297 /* initialize remt_name_not_required to false so that we get the name by 298 * default */ 299 result.inq_res.remt_name_not_required = false; 300 } 301 302 if (bta_dm_search_cb.p_device_search_cback) 303 bta_dm_search_cb.p_device_search_cback(BTA_DM_INQ_RES_EVT, &result); 304 305 if (p_inq_info) { 306 /* application indicates if it knows the remote name, inside the callback 307 copy that to the inquiry data base*/ 308 if (result.inq_res.remt_name_not_required) 309 p_inq_info->appl_knows_rem_name = true; 310 } 311 } 312 313 /******************************************************************************* 314 * 315 * Function bta_dm_remname_cback 316 * 317 * Description Remote name complete call back from BTM 318 * 319 * Returns void 320 * 321 ******************************************************************************/ 322 static void bta_dm_remname_cback(const tBTM_REMOTE_DEV_NAME* p_remote_name) { 323 log::assert_that(p_remote_name != nullptr, 324 "assert failed: p_remote_name != nullptr"); 325 326 log::info( 327 "Remote name request complete peer:{} btm_status:{} hci_status:{} " 328 "name[0]:{:c} length:{}", 329 p_remote_name->bd_addr, btm_status_text(p_remote_name->status), 330 hci_error_code_text(p_remote_name->hci_status), 331 p_remote_name->remote_bd_name[0], 332 strnlen((const char*)p_remote_name->remote_bd_name, BD_NAME_LEN)); 333 334 if (bta_dm_search_cb.peer_bdaddr != p_remote_name->bd_addr) { 335 // if we got a different response, maybe ignore it 336 // we will have made a request directly from BTM_ReadRemoteDeviceName so we 337 // expect a dedicated response for us 338 if (p_remote_name->hci_status == HCI_ERR_CONNECTION_EXISTS) { 339 log::info( 340 "Assume command failed due to disconnection hci_status:{} peer:{}", 341 hci_error_code_text(p_remote_name->hci_status), 342 p_remote_name->bd_addr); 343 } else { 344 log::info( 345 "Ignored remote name response for the wrong address exp:{} act:{}", 346 bta_dm_search_cb.peer_bdaddr, p_remote_name->bd_addr); 347 return; 348 } 349 } 350 351 /* remote name discovery is done but it could be failed */ 352 bta_dm_search_cb.name_discover_done = true; 353 bd_name_copy(bta_dm_search_cb.peer_name, p_remote_name->remote_bd_name); 354 355 auto msg = std::make_unique<tBTA_DM_SEARCH_MSG>(tBTA_DM_REMOTE_NAME{}); 356 auto& rmt_name_msg = std::get<tBTA_DM_REMOTE_NAME>(*msg); 357 rmt_name_msg.bd_addr = bta_dm_search_cb.peer_bdaddr; 358 rmt_name_msg.hci_status = p_remote_name->hci_status; 359 bd_name_copy(rmt_name_msg.bd_name, p_remote_name->remote_bd_name); 360 361 post_search_evt(BTA_DM_REMT_NAME_EVT, std::move(msg)); 362 } 363 364 /******************************************************************************* 365 * 366 * Function bta_dm_read_remote_device_name 367 * 368 * Description Initiate to get remote device name 369 * 370 * Returns true if started to get remote name 371 * 372 ******************************************************************************/ 373 static bool bta_dm_read_remote_device_name(const RawAddress& bd_addr, 374 tBT_TRANSPORT transport) { 375 tBTM_STATUS btm_status; 376 377 log::verbose(""); 378 379 bta_dm_search_cb.peer_bdaddr = bd_addr; 380 bta_dm_search_cb.peer_name[0] = 0; 381 382 btm_status = get_btm_client_interface().peer.BTM_ReadRemoteDeviceName( 383 bta_dm_search_cb.peer_bdaddr, bta_dm_remname_cback, transport); 384 385 if (btm_status == BTM_CMD_STARTED) { 386 log::verbose("BTM_ReadRemoteDeviceName is started"); 387 388 return (true); 389 } else if (btm_status == BTM_BUSY) { 390 log::verbose("BTM_ReadRemoteDeviceName is busy"); 391 392 return (true); 393 } else { 394 log::warn("BTM_ReadRemoteDeviceName returns 0x{:02X}", btm_status); 395 396 return (false); 397 } 398 } 399 400 /******************************************************************************* 401 * 402 * Function bta_dm_inq_cmpl 403 * 404 * Description Process the inquiry complete event from BTM 405 * 406 * Returns void 407 * 408 ******************************************************************************/ 409 static void bta_dm_inq_cmpl() { 410 if (bta_dm_search_get_state() == BTA_DM_SEARCH_CANCELLING) { 411 bta_dm_search_set_state(BTA_DM_SEARCH_IDLE); 412 bta_dm_execute_queued_search_request(); 413 return; 414 } 415 416 if (bta_dm_search_get_state() != BTA_DM_SEARCH_ACTIVE) { 417 return; 418 } 419 420 log::verbose("bta_dm_inq_cmpl"); 421 422 bta_dm_search_cb.p_btm_inq_info = 423 get_btm_client_interface().db.BTM_InqDbFirst(); 424 if (bta_dm_search_cb.p_btm_inq_info != NULL) { 425 /* start name discovery from the first device on inquiry result 426 */ 427 bta_dm_search_cb.name_discover_done = false; 428 bta_dm_search_cb.peer_name[0] = 0; 429 bta_dm_discover_name( 430 bta_dm_search_cb.p_btm_inq_info->results.remote_bd_addr); 431 } else { 432 bta_dm_search_cmpl(); 433 } 434 } 435 436 static void bta_dm_remote_name_cmpl( 437 const tBTA_DM_REMOTE_NAME& remote_name_msg) { 438 BTM_LogHistory(kBtmLogTag, remote_name_msg.bd_addr, "Remote name completed", 439 base::StringPrintf( 440 "status:%s state:%s name:\"%s\"", 441 hci_status_code_text(remote_name_msg.hci_status).c_str(), 442 bta_dm_state_text(bta_dm_search_get_state()).c_str(), 443 PRIVATE_NAME(remote_name_msg.bd_name))); 444 445 tBTM_INQ_INFO* p_btm_inq_info = 446 get_btm_client_interface().db.BTM_InqDbRead(remote_name_msg.bd_addr); 447 if (!bd_name_is_empty(remote_name_msg.bd_name) && p_btm_inq_info) { 448 #ifdef OPLUS_FEATURE_BT_HS_INQUIRY 449 //lvshengyi@CONNECTIVITY.BT.Basic.Inquiry.1653415, 2021/03/09 450 //If the Bluetooth device used as RNR has no name before, the address and name information of the device 451 //will be cached to the local file 452 std::string namestr((char*)remote_name_msg.bd_name); 453 log::debug("bta_dm_rmt_name: {},inq_num: {}", 454 obfuscate_name_string(namestr), 455 btm_cb.btm_inq_vars.inq_num); 456 oplus_save_rnr_info_to_file(remote_name_msg.bd_addr,(char*)remote_name_msg.bd_name, 457 bta_dm_search_cb.p_btm_inq_info->appl_knows_rem_name); 458 #endif/*OPLUS_FEATURE_BT_HS_INQUIRY*/ 459 p_btm_inq_info->appl_knows_rem_name = true; 460 } 461 462 // Callback with this property 463 if (bta_dm_search_cb.p_device_search_cback != nullptr) { 464 tBTA_DM_SEARCH search_data = { 465 .name_res = {.bd_addr = remote_name_msg.bd_addr, .bd_name = {}}, 466 }; 467 if (remote_name_msg.hci_status == HCI_SUCCESS) { 468 bd_name_copy(search_data.name_res.bd_name, remote_name_msg.bd_name); 469 } 470 bta_dm_search_cb.p_device_search_cback(BTA_DM_NAME_READ_EVT, &search_data); 471 } else { 472 log::warn("Received remote name complete without callback"); 473 } 474 475 switch (bta_dm_search_get_state()) { 476 case BTA_DM_SEARCH_ACTIVE: 477 bta_dm_discover_name(bta_dm_search_cb.peer_bdaddr); 478 break; 479 case BTA_DM_SEARCH_IDLE: 480 case BTA_DM_SEARCH_CANCELLING: 481 log::warn("Received remote name request in state:{}", 482 bta_dm_state_text(bta_dm_search_get_state())); 483 break; 484 } 485 } 486 487 static void bta_dm_search_cmpl() { 488 bta_dm_search_set_state(BTA_DM_SEARCH_IDLE); 489 490 if (bta_dm_search_cb.p_device_search_cback) { 491 bta_dm_search_cb.p_device_search_cback(BTA_DM_DISC_CMPL_EVT, nullptr); 492 } 493 494 bta_dm_execute_queued_search_request(); 495 } 496 497 static void bta_dm_execute_queued_search_request() { 498 if (!bta_dm_search_cb.p_pending_search) return; 499 500 log::info("Start pending search"); 501 post_search_evt(BTA_DM_API_SEARCH_EVT, 502 std::move(bta_dm_search_cb.p_pending_search)); 503 bta_dm_search_cb.p_pending_search.reset(); 504 } 505 506 /******************************************************************************* 507 * 508 * Function bta_dm_search_clear_queue 509 * 510 * Description Clears the queue if API search cancel is called 511 * 512 * Returns void 513 * 514 ******************************************************************************/ 515 static void bta_dm_search_clear_queue() { 516 bta_dm_search_cb.p_pending_search.reset(); 517 } 518 519 /******************************************************************************* 520 * 521 * Function bta_dm_search_cancel_notify 522 * 523 * Description Notify application that search has been cancelled 524 * 525 * Returns void 526 * 527 ******************************************************************************/ 528 static void bta_dm_search_cancel_notify() { 529 if (bta_dm_search_cb.p_device_search_cback) { 530 bta_dm_search_cb.p_device_search_cback(BTA_DM_SEARCH_CANCEL_CMPL_EVT, NULL); 531 } 532 switch (bta_dm_search_get_state()) { 533 case BTA_DM_SEARCH_ACTIVE: 534 case BTA_DM_SEARCH_CANCELLING: 535 if (!bta_dm_search_cb.name_discover_done) { 536 if (get_btm_client_interface().peer.BTM_CancelRemoteDeviceName() != 537 BTM_CMD_STARTED) { 538 log::warn("Unable to cancel RNR"); 539 } 540 } 541 break; 542 case BTA_DM_SEARCH_IDLE: 543 // Nothing to do 544 break; 545 } 546 } 547 548 /******************************************************************************* 549 * 550 * Function bta_dm_discover_next_device 551 * 552 * Description Starts discovery on the next device in Inquiry data base 553 * 554 * Returns void 555 * 556 ******************************************************************************/ 557 static void bta_dm_discover_next_device(void) { 558 log::verbose("bta_dm_discover_next_device"); 559 560 /* searching next device on inquiry result */ 561 bta_dm_search_cb.p_btm_inq_info = get_btm_client_interface().db.BTM_InqDbNext( 562 bta_dm_search_cb.p_btm_inq_info); 563 if (bta_dm_search_cb.p_btm_inq_info != NULL) { 564 bta_dm_search_cb.name_discover_done = false; 565 bta_dm_search_cb.peer_name[0] = 0; 566 bta_dm_discover_name( 567 bta_dm_search_cb.p_btm_inq_info->results.remote_bd_addr); 568 } else { 569 post_search_evt(BTA_DM_SEARCH_CMPL_EVT, nullptr); 570 } 571 } 572 573 /*TODO: this function is duplicated, make it common ?*/ 574 static tBT_TRANSPORT bta_dm_determine_discovery_transport( 575 const RawAddress& remote_bd_addr) { 576 tBT_DEVICE_TYPE dev_type; 577 tBLE_ADDR_TYPE addr_type; 578 579 get_btm_client_interface().peer.BTM_ReadDevInfo(remote_bd_addr, &dev_type, 580 &addr_type); 581 if (dev_type == BT_DEVICE_TYPE_BLE || addr_type == BLE_ADDR_RANDOM) { 582 return BT_TRANSPORT_LE; 583 } else if (dev_type == BT_DEVICE_TYPE_DUMO) { 584 if (get_btm_client_interface().peer.BTM_IsAclConnectionUp( 585 remote_bd_addr, BT_TRANSPORT_BR_EDR)) { 586 return BT_TRANSPORT_BR_EDR; 587 } else if (get_btm_client_interface().peer.BTM_IsAclConnectionUp( 588 remote_bd_addr, BT_TRANSPORT_LE)) { 589 return BT_TRANSPORT_LE; 590 } 591 } 592 return BT_TRANSPORT_BR_EDR; 593 } 594 595 static void bta_dm_discover_name(const RawAddress& remote_bd_addr) { 596 const tBT_TRANSPORT transport = 597 bta_dm_determine_discovery_transport(remote_bd_addr); 598 599 log::verbose("BDA: {}", remote_bd_addr); 600 601 bta_dm_search_cb.peer_bdaddr = remote_bd_addr; 602 603 log::verbose( 604 "name_discover_done = {} p_btm_inq_info 0x{} state = {}, transport={}", 605 bta_dm_search_cb.name_discover_done, 606 fmt::ptr(bta_dm_search_cb.p_btm_inq_info), bta_dm_search_get_state(), 607 transport); 608 609 if (bta_dm_search_cb.p_btm_inq_info) { 610 log::verbose("appl_knows_rem_name {}", 611 bta_dm_search_cb.p_btm_inq_info->appl_knows_rem_name); 612 } 613 /** M: Avoid initiate RNR to LE transport. @{ */ 614 if (((bta_dm_search_cb.p_btm_inq_info) && 615 (bta_dm_search_cb.p_btm_inq_info->results.device_type == 616 BT_DEVICE_TYPE_BLE) && 617 #ifndef OPLUS_FEATURE_BT_LE_AUDIO 618 (bta_dm_search_get_state() == BTA_DM_SEARCH_ACTIVE)) || 619 transport == BT_TRANSPORT_LE && 620 interop_match_addr(INTEROP_DISABLE_NAME_REQUEST, 621 &bta_dm_search_cb.peer_bdaddr))) { 622 #else 623 (bta_dm_search_get_state() == BTA_DM_SEARCH_ACTIVE)) || 624 (transport == BT_TRANSPORT_LE && (!is_device_le_audio_capable(remote_bd_addr)))) { 625 #endif /* OPLUS_FEATURE_BT_LE_AUDIO */ 626 /** @} */ 627 /* Do not perform RNR for LE devices at inquiry complete*/ 628 bta_dm_search_cb.name_discover_done = true; 629 } 630 631 #ifdef OPLUS_FEATURE_BT_HS_INQUIRY 632 //lvshengyi@CONNECTIVITY.BT.Basic.Inquiry.1653415, 2021/03/09 633 if(bta_dm_search_cb.p_btm_inq_info) { 634 bta_dm_search_cb.name_discover_done = oplus_check_remote_device_not_need_rnr( 635 //#ifdef OPLUS_FEATURE_BT_LE_AUDIO 636 //wangli@CONNECTIVITY.BT.Basic.FEATURE.5308163, add acl exist, if exist to read remote name for BLE 637 remote_bd_addr, btm_cb.btm_inq_vars.inq_num, bta_dm_search_cb.p_btm_inq_info->results.rssi); 638 //#endif /*OPLUS_FEATURE_BT_LE_AUDIO*/ 639 if(!bta_dm_search_cb.name_discover_done) { 640 LOG_VERBOSE("%s rssi: %d ,inq_num: %d", __func__, 641 bta_dm_search_cb.p_btm_inq_info->results.rssi, 642 btm_cb.btm_inq_vars.inq_num); 643 } 644 } 645 #endif /*OPLUS_FEATURE_BT_HS_INQUIRY*/ 646 647 // If we already have the name we can skip getting the name 648 if (BTM_IsRemoteNameKnown(remote_bd_addr, transport) && 649 bluetooth::common::init_flags::sdp_skip_rnr_if_known_is_enabled()) { 650 log::debug( 651 "Security record already known skipping read remote name peer:{}", 652 remote_bd_addr); 653 bta_dm_search_cb.name_discover_done = true; 654 } 655 656 /* if name discovery is not done and application needs remote name */ 657 if ((!bta_dm_search_cb.name_discover_done) && 658 ((bta_dm_search_cb.p_btm_inq_info == NULL) || 659 (bta_dm_search_cb.p_btm_inq_info && 660 (!bta_dm_search_cb.p_btm_inq_info->appl_knows_rem_name)))) { 661 if (bta_dm_read_remote_device_name(bta_dm_search_cb.peer_bdaddr, 662 transport)) { 663 BTM_LogHistory(kBtmLogTag, bta_dm_search_cb.peer_bdaddr, 664 "Read remote name", 665 base::StringPrintf("Transport:%s", 666 bt_transport_text(transport).c_str())); 667 return; 668 } else { 669 log::error("Unable to start read remote device name"); 670 } 671 672 /* starting name discovery failed */ 673 bta_dm_search_cb.name_discover_done = true; 674 } 675 676 /* name discovery is done for this device */ 677 if (bta_dm_search_get_state() == BTA_DM_SEARCH_ACTIVE) { 678 // if p_btm_inq_info is nullptr, there is no more inquiry results to 679 // discover name for 680 if (bta_dm_search_cb.p_btm_inq_info) { 681 bta_dm_discover_next_device(); 682 } else { 683 log::info("end of parsing inquiry result"); 684 } 685 } else { 686 log::info("name discovery finished in bad state: {}", 687 bta_dm_state_text(bta_dm_search_get_state())); 688 } 689 } 690 691 /******************************************************************************* 692 * 693 * Function bta_dm_is_search_request_queued 694 * 695 * Description Checks if there is a queued search request 696 * 697 * Returns bool 698 * 699 ******************************************************************************/ 700 bool bta_dm_is_search_request_queued() { 701 if (!com::android::bluetooth::flags:: 702 separate_service_and_device_discovery()) { 703 return bta_dm_disc_legacy::bta_dm_is_search_request_queued(); 704 } 705 return bta_dm_search_cb.p_pending_search != NULL; 706 } 707 708 /******************************************************************************* 709 * 710 * Function bta_dm_queue_search 711 * 712 * Description Queues search command 713 * 714 * Returns void 715 * 716 ******************************************************************************/ 717 static void bta_dm_queue_search(tBTA_DM_API_SEARCH& search) { 718 if (bta_dm_search_cb.p_pending_search) { 719 log::warn("Overwrote previous device discovery inquiry scan request"); 720 } 721 bta_dm_search_cb.p_pending_search.reset(new tBTA_DM_SEARCH_MSG(search)); 722 log::info("Queued device discovery inquiry scan request"); 723 } 724 725 /******************************************************************************* 726 * 727 * Function bta_dm_observe_results_cb 728 * 729 * Description Callback for BLE Observe result 730 * 731 * 732 * Returns void 733 * 734 ******************************************************************************/ 735 static void bta_dm_observe_results_cb(tBTM_INQ_RESULTS* p_inq, 736 const uint8_t* p_eir, uint16_t eir_len) { 737 tBTA_DM_SEARCH result; 738 tBTM_INQ_INFO* p_inq_info; 739 log::verbose("bta_dm_observe_results_cb"); 740 741 result.inq_res.bd_addr = p_inq->remote_bd_addr; 742 result.inq_res.original_bda = p_inq->original_bda; 743 result.inq_res.rssi = p_inq->rssi; 744 result.inq_res.ble_addr_type = p_inq->ble_addr_type; 745 result.inq_res.inq_result_type = p_inq->inq_result_type; 746 result.inq_res.device_type = p_inq->device_type; 747 result.inq_res.flag = p_inq->flag; 748 result.inq_res.ble_evt_type = p_inq->ble_evt_type; 749 result.inq_res.ble_primary_phy = p_inq->ble_primary_phy; 750 result.inq_res.ble_secondary_phy = p_inq->ble_secondary_phy; 751 result.inq_res.ble_advertising_sid = p_inq->ble_advertising_sid; 752 result.inq_res.ble_tx_power = p_inq->ble_tx_power; 753 result.inq_res.ble_periodic_adv_int = p_inq->ble_periodic_adv_int; 754 755 /* application will parse EIR to find out remote device name */ 756 result.inq_res.p_eir = const_cast<uint8_t*>(p_eir); 757 result.inq_res.eir_len = eir_len; 758 759 p_inq_info = 760 get_btm_client_interface().db.BTM_InqDbRead(p_inq->remote_bd_addr); 761 if (p_inq_info != NULL) { 762 /* initialize remt_name_not_required to false so that we get the name by 763 * default */ 764 result.inq_res.remt_name_not_required = false; 765 } 766 767 if (p_inq_info) { 768 /* application indicates if it knows the remote name, inside the callback 769 copy that to the inquiry data base*/ 770 if (result.inq_res.remt_name_not_required) 771 p_inq_info->appl_knows_rem_name = true; 772 } 773 } 774 775 /******************************************************************************* 776 * 777 * Function bta_dm_opportunistic_observe_results_cb 778 * 779 * Description Callback for BLE Observe result 780 * 781 * 782 * Returns void 783 * 784 ******************************************************************************/ 785 static void bta_dm_opportunistic_observe_results_cb(tBTM_INQ_RESULTS* p_inq, 786 const uint8_t* p_eir, 787 uint16_t eir_len) { 788 tBTA_DM_SEARCH result; 789 tBTM_INQ_INFO* p_inq_info; 790 791 result.inq_res.bd_addr = p_inq->remote_bd_addr; 792 result.inq_res.rssi = p_inq->rssi; 793 result.inq_res.ble_addr_type = p_inq->ble_addr_type; 794 result.inq_res.inq_result_type = p_inq->inq_result_type; 795 result.inq_res.device_type = p_inq->device_type; 796 result.inq_res.flag = p_inq->flag; 797 result.inq_res.ble_evt_type = p_inq->ble_evt_type; 798 result.inq_res.ble_primary_phy = p_inq->ble_primary_phy; 799 result.inq_res.ble_secondary_phy = p_inq->ble_secondary_phy; 800 result.inq_res.ble_advertising_sid = p_inq->ble_advertising_sid; 801 result.inq_res.ble_tx_power = p_inq->ble_tx_power; 802 result.inq_res.ble_periodic_adv_int = p_inq->ble_periodic_adv_int; 803 804 /* application will parse EIR to find out remote device name */ 805 result.inq_res.p_eir = const_cast<uint8_t*>(p_eir); 806 result.inq_res.eir_len = eir_len; 807 808 p_inq_info = 809 get_btm_client_interface().db.BTM_InqDbRead(p_inq->remote_bd_addr); 810 if (p_inq_info != NULL) { 811 /* initialize remt_name_not_required to false so that we get the name by 812 * default */ 813 result.inq_res.remt_name_not_required = false; 814 } 815 816 if (bta_dm_search_cb.p_csis_scan_cback) 817 bta_dm_search_cb.p_csis_scan_cback(BTA_DM_INQ_RES_EVT, &result); 818 819 if (p_inq_info) { 820 /* application indicates if it knows the remote name, inside the callback 821 copy that to the inquiry data base*/ 822 if (result.inq_res.remt_name_not_required) 823 p_inq_info->appl_knows_rem_name = true; 824 } 825 } 826 827 /******************************************************************************* 828 * 829 * Function bta_dm_observe_cmpl_cb 830 * 831 * Description Callback for BLE Observe complete 832 * 833 * 834 * Returns void 835 * 836 ******************************************************************************/ 837 static void bta_dm_observe_cmpl_cb(void* p_result) { 838 log::verbose("bta_dm_observe_cmpl_cb"); 839 840 if (bta_dm_search_cb.p_csis_scan_cback) { 841 auto num_resps = ((tBTM_INQUIRY_CMPL*)p_result)->num_resp; 842 tBTA_DM_SEARCH data{.observe_cmpl{.num_resps = num_resps}}; 843 bta_dm_search_cb.p_csis_scan_cback(BTA_DM_OBSERVE_CMPL_EVT, &data); 844 } 845 } 846 847 static void bta_dm_start_scan(uint8_t duration_sec, 848 bool low_latency_scan = false) { 849 tBTM_STATUS status = get_btm_client_interface().ble.BTM_BleObserve( 850 true, duration_sec, bta_dm_observe_results_cb, bta_dm_observe_cmpl_cb, 851 low_latency_scan); 852 853 if (status != BTM_CMD_STARTED) { 854 log::warn("BTM_BleObserve failed. status {}", status); 855 if (bta_dm_search_cb.p_csis_scan_cback) { 856 tBTA_DM_SEARCH data{.observe_cmpl = {.num_resps = 0}}; 857 bta_dm_search_cb.p_csis_scan_cback(BTA_DM_OBSERVE_CMPL_EVT, &data); 858 } 859 } 860 } 861 862 void bta_dm_ble_scan(bool start, uint8_t duration_sec, 863 bool low_latency_scan = false) { 864 if (!start) { 865 if (get_btm_client_interface().ble.BTM_BleObserve( 866 false, 0, NULL, NULL, false) != BTM_CMD_STARTED) { 867 log::warn("Unable to start ble observe"); 868 } 869 return; 870 } 871 872 bta_dm_start_scan(duration_sec, low_latency_scan); 873 } 874 875 void bta_dm_ble_csis_observe(bool observe, tBTA_DM_SEARCH_CBACK* p_cback) { 876 if (!observe) { 877 bta_dm_search_cb.p_csis_scan_cback = NULL; 878 BTM_BleOpportunisticObserve(false, NULL); 879 return; 880 } 881 882 /* Save the callback to be called when a scan results are available */ 883 bta_dm_search_cb.p_csis_scan_cback = p_cback; 884 BTM_BleOpportunisticObserve(true, bta_dm_opportunistic_observe_results_cb); 885 } 886 887 namespace bluetooth { 888 namespace legacy { 889 namespace testing { 890 891 void bta_dm_remname_cback(const tBTM_REMOTE_DEV_NAME* p) { 892 ::bta_dm_remname_cback(p); 893 } 894 895 void bta_dm_remote_name_cmpl(const tBTA_DM_REMOTE_NAME& remote_name_msg) { 896 ::bta_dm_remote_name_cmpl(remote_name_msg); 897 } 898 899 } // namespace testing 900 } // namespace legacy 901 } // namespace bluetooth 902 903 namespace { 904 constexpr size_t kSearchStateHistorySize = 50; 905 constexpr char kTimeFormatString[] = "%Y-%m-%d %H:%M:%S"; 906 907 constexpr unsigned MillisPerSecond = 1000; 908 std::string EpochMillisToString(long long time_ms) { 909 time_t time_sec = time_ms / MillisPerSecond; 910 struct tm tm; 911 localtime_r(&time_sec, &tm); 912 std::string s = bluetooth::common::StringFormatTime(kTimeFormatString, tm); 913 return base::StringPrintf( 914 "%s.%03u", s.c_str(), 915 static_cast<unsigned int>(time_ms % MillisPerSecond)); 916 } 917 918 } // namespace 919 920 struct tSEARCH_STATE_HISTORY { 921 const tBTA_DM_DEVICE_SEARCH_STATE state; 922 const tBTA_DM_DEV_SEARCH_EVT event; 923 std::string ToString() const { 924 return base::StringPrintf("state:%25s event:%s", 925 bta_dm_state_text(state).c_str(), 926 bta_dm_event_text(event).c_str()); 927 } 928 }; 929 930 bluetooth::common::TimestampedCircularBuffer<tSEARCH_STATE_HISTORY> 931 search_state_history_(kSearchStateHistorySize); 932 933 /******************************************************************************* 934 * 935 * Function bta_dm_search_sm_execute 936 * 937 * Description State machine event handling function for DM 938 * 939 * 940 * Returns void 941 * 942 ******************************************************************************/ 943 static void bta_dm_search_sm_execute(tBTA_DM_DEV_SEARCH_EVT event, 944 std::unique_ptr<tBTA_DM_SEARCH_MSG> msg) { 945 log::info("state:{}, event:{}[0x{:x}]", 946 bta_dm_state_text(bta_dm_search_get_state()), 947 bta_dm_event_text(event), event); 948 search_state_history_.Push({ 949 .state = bta_dm_search_get_state(), 950 .event = event, 951 }); 952 953 switch (bta_dm_search_get_state()) { 954 case BTA_DM_SEARCH_IDLE: 955 switch (event) { 956 case BTA_DM_API_SEARCH_EVT: 957 bta_dm_search_set_state(BTA_DM_SEARCH_ACTIVE); 958 log::assert_that(std::holds_alternative<tBTA_DM_API_SEARCH>(*msg), 959 "bad message type: {}", msg->index()); 960 961 bta_dm_search_start(std::get<tBTA_DM_API_SEARCH>(*msg)); 962 break; 963 case BTA_DM_API_SEARCH_CANCEL_EVT: 964 bta_dm_search_clear_queue(); 965 bta_dm_search_cancel_notify(); 966 break; 967 default: 968 log::info("Received unexpected event {}[0x{:x}] in state {}", 969 bta_dm_event_text(event), event, 970 bta_dm_state_text(bta_dm_search_get_state())); 971 } 972 break; 973 case BTA_DM_SEARCH_ACTIVE: 974 switch (event) { 975 case BTA_DM_REMT_NAME_EVT: 976 log::assert_that(std::holds_alternative<tBTA_DM_REMOTE_NAME>(*msg), 977 "bad message type: {}", msg->index()); 978 979 bta_dm_remote_name_cmpl(std::get<tBTA_DM_REMOTE_NAME>(*msg)); 980 break; 981 case BTA_DM_SEARCH_CMPL_EVT: 982 bta_dm_search_cmpl(); 983 break; 984 case BTA_DM_API_SEARCH_CANCEL_EVT: 985 bta_dm_search_clear_queue(); 986 bta_dm_search_set_state(BTA_DM_SEARCH_CANCELLING); 987 bta_dm_search_cancel(); 988 break; 989 default: 990 log::info("Received unexpected event {}[0x{:x}] in state {}", 991 bta_dm_event_text(event), event, 992 bta_dm_state_text(bta_dm_search_get_state())); 993 } 994 break; 995 case BTA_DM_SEARCH_CANCELLING: 996 switch (event) { 997 case BTA_DM_API_SEARCH_EVT: 998 log::assert_that(std::holds_alternative<tBTA_DM_API_SEARCH>(*msg), 999 "bad message type: {}", msg->index()); 1000 1001 bta_dm_queue_search(std::get<tBTA_DM_API_SEARCH>(*msg)); 1002 break; 1003 case BTA_DM_API_SEARCH_CANCEL_EVT: 1004 bta_dm_search_clear_queue(); 1005 bta_dm_search_cancel_notify(); 1006 break; 1007 case BTA_DM_REMT_NAME_EVT: 1008 case BTA_DM_SEARCH_CMPL_EVT: 1009 bta_dm_search_set_state(BTA_DM_SEARCH_IDLE); 1010 bta_dm_search_cancel_notify(); 1011 bta_dm_execute_queued_search_request(); 1012 break; 1013 default: 1014 log::info("Received unexpected event {}[0x{:x}] in state {}", 1015 bta_dm_event_text(event), event, 1016 bta_dm_state_text(bta_dm_search_get_state())); 1017 } 1018 break; 1019 } 1020 } 1021 1022 static void bta_dm_disable_search(void) { 1023 switch (bta_dm_search_get_state()) { 1024 case BTA_DM_SEARCH_IDLE: 1025 break; 1026 case BTA_DM_SEARCH_ACTIVE: 1027 case BTA_DM_SEARCH_CANCELLING: 1028 default: 1029 log::debug( 1030 "Search state machine is not idle so issuing search cancel current " 1031 "state:{}", 1032 bta_dm_state_text(bta_dm_search_get_state())); 1033 bta_dm_search_cancel(); 1034 } 1035 } 1036 1037 void bta_dm_disc_start_device_discovery(tBTA_DM_SEARCH_CBACK* p_cback) { 1038 if (!com::android::bluetooth::flags:: 1039 separate_service_and_device_discovery()) { 1040 bta_dm_disc_legacy::bta_dm_disc_start_device_discovery(p_cback); 1041 return; 1042 } 1043 bta_dm_search_sm_execute(BTA_DM_API_SEARCH_EVT, 1044 std::make_unique<tBTA_DM_SEARCH_MSG>( 1045 tBTA_DM_API_SEARCH{.p_cback = p_cback})); 1046 } 分析一下这段代码的逻辑
09-02
xref: /MT6769_15.0.0_release/vnd/vendor/mediatek/proprietary/bootable/bootloader/lk/platform/mt6768/platform.c HomeAnnotateLine# Scopes# Navigate#Raw Download current directory 1 /* Copyright Statement: 2 * 3 * This software/firmware and related documentation ("MediaTek Software") are 4 * protected under relevant copyright laws. The information contained herein 5 * is confidential and proprietary to MediaTek Inc. and/or its licensors. 6 * Without the prior written permission of MediaTek inc. and/or its licensors, 7 * any reproduction, modification, use or disclosure of MediaTek Software, 8 * and information contained herein, in whole or in part, shall be strictly prohibited. 9 */ 10 /* MediaTek Inc. (C) 2015. All rights reserved. 11 * 12 * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES 13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") 14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON 15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. 18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE 19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR 20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH 21 * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES 22 * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES 23 * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK 24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR 25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND 26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, 27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, 28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO 29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 30 */ 31 32 #include <debug.h> 33 #include <stdlib.h> 34 #include <string.h> 35 #include <video.h> 36 #include <dev/uart.h> 37 #include <arch/arm.h> 38 #include <arch/arm/mmu.h> 39 #include <arch/ops.h> 40 #include <target/board.h> 41 #include <platform/mt_reg_base.h> 42 #include <platform/mt_disp_drv.h> 43 #include <platform/disp_drv.h> 44 #include <platform/boot_mode.h> 45 #include <platform/mt_logo.h> 46 #include <platform/partition.h> 47 #include <env.h> 48 #include <platform/mt_gpio.h> 49 #include <platform/mt_pmic.h> 50 #include <platform/mt_pmic_dlpt.h> 51 #include <platform/mt_pmic_wrap_init.h> 52 #include <platform/mt_i2c.h> 53 #include <spi_slave.h> 54 #include <platform/mtk_key.h> 55 #include <platform/mtk_smi.h> 56 #include <platform/mt_rtc.h> 57 #include <platform/mt_leds.h> 58 #include <platform/upmu_common.h> 59 #include <mtk_wdt.h> 60 #include <platform/disp_drv_platform.h> 61 #include <platform/verified_boot.h> 62 #include <platform/sec_devinfo.h> 63 #include <plinfo.h> // for plinfo_get_brom_header_block_size() 64 #include <libfdt.h> 65 #include <mt_gic.h> // for platform_init_interrupts() 66 #include <mt_boot.h> // for bldr_load_dtb() 67 #include <mtk_dcm.h> // for mt_dcm_init() 68 #include <fpga_boot_argument.h> 69 #include <profiling.h> 70 #include <assert.h> 71 #include <platform/mt_gpt.h> // for get_timer() 72 #include <sec_export.h> 73 #include "memory_layout.h" 74 #include "load_vfy_boot.h" 75 #include <fdt_op.h> 76 #include <verified_boot_common.h> 77 #include <platform/mtk_charger_intf.h> 78 #include <rsc.h> 79 #ifdef MTK_SMC_ID_MGMT 80 #include "mtk_secure_api.h" 81 #endif 82 #include "mtk_dcm.h" //for mt_dcm_init() 83 #ifdef MTK_EMMC_SUPPORT 84 #include "mmc_rpmb.h" 85 #endif 86 87 #define DEVAPC_TURN_ON 1 88 89 //like@BSP.Storage.EMMC, 2022/11/25 add for getting emmc health info 90 #include "emmc_health_info.h" 91 //like@BSP.Storage.Emmc, 2022/11/25 add for emmc fw upgrade 92 #include "emmc_upgrade.h" 93 #ifdef MTK_UFS_SUPPORT 94 //like@BSP.Storage.UFS, 2022/11/25 add for emmc/ufs compatible 95 #include "ufs_upgrade.h" 96 #endif 97 #if defined(MTK_VPU_SUPPORT) 98 #include <platform/mt_vpu.h> 99 #endif 100 101 #ifdef MTK_AB_OTA_UPDATER 102 #include "bootctrl.h" 103 #endif 104 105 #if defined(MTK_SECURITY_SW_SUPPORT) 106 #include "oemkey.h" 107 #endif 108 #ifdef MTK_UFS_SUPPORT 109 #include "ufs_aio_interface.h" 110 #endif 111 112 #ifdef MTK_CHARGER_NEW_ARCH 113 #include <mtk_charger.h> 114 #include <mtk_battery.h> 115 #endif 116 #include "show_animation_common.h" 117 118 #ifdef MTK_SECURITY_SW_SUPPORT 119 extern u8 g_oemkey[OEM_PUBK_SZ]; 120 #endif 121 122 #ifdef LK_DL_CHECK 123 /*block if check dl fail*/ 124 #undef LK_DL_CHECK_BLOCK_LEVEL 125 #endif 126 127 #ifdef OPLUS_FEATURE_CHG_BASIC 128 #define VIB_BOOT_THRESHOLD_MV 3200 129 #define VIB_DURATION 300 130 #endif 131 132 extern void platform_early_init_timer(); 133 extern void jump_da(u32 addr, u32 arg1, u32 arg2); 134 extern int i2c_hw_init(void); 135 extern int mboot_common_load_logo(unsigned long logo_addr, char* filename); 136 extern int sec_func_init(u64 pl_start_addr); 137 extern int sec_usbdl_enabled (void); 138 extern unsigned int crypto_hw_engine_disable(void); 139 extern void mtk_wdt_disable(void); 140 extern void platform_deinit_interrupts(void); 141 extern int mmc_get_dl_info(void); 142 extern int mmc_legacy_init(int); 143 extern void platform_clear_all_on_mux(void); 144 extern unsigned int crypto_hw_engine_disable(void); 145 #ifdef MTK_AEE_PLATFORM_DEBUG_SUPPORT 146 extern void latch_lastbus_init(void); 147 #endif 148 149 #ifdef MTK_BATLOWV_NO_PANEL_ON_EARLY 150 extern kal_bool is_low_battery(kal_int32 val); 151 extern int hw_charging_get_charger_type(void); 152 #endif 153 154 #ifdef MTK_LK_REGISTER_WDT 155 extern void lk_register_wdt_callback(void); 156 #endif 157 158 void platform_uninit(void); 159 void config_shared_SRAM_size(void); 160 extern int dev_info_nr_cpu(void); 161 extern void mt_pll_turn_off(void); 162 163 struct mmu_initial_mapping mmu_initial_mappings[] = { 164 165 { 166 .phys = (uint64_t)0, 167 .virt = (uint32_t)0, 168 .size = 0x40000000, 169 .flags = MMU_MEMORY_TYPE_STRONGLY_ORDERED | MMU_MEMORY_AP_P_RW_U_NA, 170 .name = "mcusys" 171 }, 172 { 173 .phys = (uint64_t)MEMBASE, 174 .virt = (uint32_t)MEMBASE, 175 .size = ROUNDUP(MEMSIZE, SECTION_SIZE), 176 .flags = MMU_MEMORY_TYPE_NORMAL_WRITE_BACK | MMU_MEMORY_AP_P_RW_U_NA, 177 .name = "ram" 178 }, 179 { 180 .phys = (uint64_t)SCRATCH_ADDR, 181 .virt = (uint32_t)SCRATCH_ADDR, 182 .size = SCRATCH_SIZE, 183 .flags = MMU_MEMORY_TYPE_NORMAL_WRITE_BACK | MMU_MEMORY_AP_P_RW_U_NA, 184 .name = "download" 185 }, 186 /* null entry to terminate the list */ 187 { 0 } 188 }; 189 190 BOOT_ARGUMENT *g_boot_arg; 191 BOOT_ARGUMENT boot_addr; 192 int g_nr_bank; 193 BI_DRAM bi_dram[MAX_NR_BANK]; 194 unsigned int g_fb_base; 195 unsigned int g_fb_size; 196 static int g_dram_init_ret; 197 static unsigned int bootarg_addr; 198 static unsigned int bootarg_size; 199 extern unsigned int logo_lk_t; 200 extern unsigned int boot_time; 201 unsigned int m_sec_usb_dl; 202 unsigned int m_sec_boot; 203 unsigned char m_seccfg_ac_en; 204 205 int dram_init(void) 206 { 207 unsigned int i; 208 struct boot_tag *tags; 209 210 /* Get parameters from pre-loader. Get as early as possible 211 * The address of BOOT_ARGUMENT_LOCATION will be used by Linux later 212 * So copy the parameters from BOOT_ARGUMENT_LOCATION to LK's memory region 213 */ 214 g_boot_arg = &boot_addr; 215 bootarg_addr = (unsigned int)((unsigned int *)BOOT_ARGUMENT_LOCATION); 216 bootarg_size = 0; 217 218 fpga_set_boot_argument((BOOT_ARGUMENT*)bootarg_addr); 219 220 if (*(unsigned int *)BOOT_ARGUMENT_LOCATION == BOOT_ARGUMENT_MAGIC) { 221 memcpy(g_boot_arg, (void*)BOOT_ARGUMENT_LOCATION, sizeof(BOOT_ARGUMENT)); 222 bootarg_size = sizeof(BOOT_ARGUMENT); 223 } else { 224 g_boot_arg->maggic_number = BOOT_ARGUMENT_MAGIC; 225 for (tags = (void *)BOOT_ARGUMENT_LOCATION; tags->hdr.size; tags = boot_tag_next(tags)) { 226 switch (tags->hdr.tag) { 227 case BOOT_TAG_BOOT_REASON: 228 g_boot_arg->boot_reason = tags->u.boot_reason.boot_reason; 229 break; 230 case BOOT_TAG_BOOT_MODE: 231 g_boot_arg->boot_mode = tags->u.boot_mode.boot_mode; 232 break; 233 case BOOT_TAG_META_COM: 234 g_boot_arg->meta_com_type = tags->u.meta_com.meta_com_type; 235 g_boot_arg->meta_com_id = tags->u.meta_com.meta_com_id; 236 g_boot_arg->meta_uart_port = tags->u.meta_com.meta_uart_port; 237 g_boot_arg->meta_log_disable = tags->u.meta_com.meta_log_disable; 238 g_boot_arg->fast_meta_gpio = tags->u.meta_com.fast_meta_gpio; 239 break; 240 case BOOT_TAG_LOG_COM: 241 g_boot_arg->log_port = tags->u.log_com.log_port; 242 g_boot_arg->log_baudrate = tags->u.log_com.log_baudrate; 243 g_boot_arg->log_enable = tags->u.log_com.log_enable; 244 g_boot_arg->log_dynamic_switch = tags->u.log_com.log_dynamic_switch; 245 break; 246 case BOOT_TAG_MEM: 247 g_boot_arg->dram_rank_num = tags->u.mem.dram_rank_num; 248 for (i = 0; i < tags->u.mem.dram_rank_num; i++) { 249 g_boot_arg->dram_rank_size[i] = tags->u.mem.dram_rank_size[i]; 250 } 251 g_boot_arg->mblock_info = tags->u.mem.mblock_info; 252 g_boot_arg->orig_dram_info = tags->u.mem.orig_dram_info; 253 g_boot_arg->lca_reserved_mem = tags->u.mem.lca_reserved_mem; 254 g_boot_arg->tee_reserved_mem = tags->u.mem.tee_reserved_mem; 255 break; 256 case BOOT_TAG_MD_INFO: 257 for (i = 0; i < 4; i++) { 258 g_boot_arg->md_type[i] = tags->u.md_info.md_type[i]; 259 } 260 break; 261 case BOOT_TAG_BOOT_TIME: 262 g_boot_arg->boot_time = tags->u.boot_time.boot_time; 263 break; 264 case BOOT_TAG_DA_INFO: 265 memcpy(&g_boot_arg->da_info, &tags->u.da_info.da_info, sizeof(da_info_t)); 266 break; 267 case BOOT_TAG_SEC_INFO: 268 memcpy(&g_boot_arg->sec_limit, &tags->u.sec_info.sec_limit, sizeof(SEC_LIMIT)); 269 break; 270 case BOOT_TAG_PART_NUM: 271 g_boot_arg->part_num = tags->u.part_num.part_num; 272 break; 273 case BOOT_TAG_PART_INFO: 274 g_boot_arg->part_info = tags->u.part_info.part_info; /* only copy the pointer but the contains*/ 275 break; 276 case BOOT_TAG_EFLAG: 277 g_boot_arg->e_flag = tags->u.eflag.e_flag; 278 break; 279 case BOOT_TAG_DDR_RESERVE: 280 g_boot_arg->ddr_reserve_enable = tags->u.ddr_reserve.ddr_reserve_enable; 281 g_boot_arg->ddr_reserve_success = tags->u.ddr_reserve.ddr_reserve_success; 282 g_boot_arg->ddr_reserve_ready = tags->u.ddr_reserve.ddr_reserve_ready; 283 break; 284 case BOOT_TAG_DRAM_BUF: 285 g_boot_arg->dram_buf_size = tags->u.dram_buf.dram_buf_size; 286 break; 287 case BOOT_TAG_SRAM_INFO: 288 g_boot_arg->non_secure_sram_addr = tags->u.sram_info.non_secure_sram_addr; 289 g_boot_arg->non_secure_sram_size = tags->u.sram_info.non_secure_sram_size; 290 break; 291 case BOOT_TAG_PLAT_DBG_INFO: 292 g_boot_arg->plat_dbg_info_max = tags->u.plat_dbg_info.info_max; 293 if (g_boot_arg->plat_dbg_info_max > INFO_TYPE_MAX) 294 g_boot_arg->plat_dbg_info_max = INFO_TYPE_MAX; 295 for (i = 0; i < g_boot_arg->plat_dbg_info_max; i++) { 296 g_boot_arg->plat_dbg_info[i].key = tags->u.plat_dbg_info.info[i].key; 297 g_boot_arg->plat_dbg_info[i].base = tags->u.plat_dbg_info.info[i].base; 298 g_boot_arg->plat_dbg_info[i].size = tags->u.plat_dbg_info.info[i].size; 299 } 300 break; 301 case BOOT_TAG_PTP: 302 memcpy(&g_boot_arg->ptp_volt_info, &tags->u.ptp_volt.ptp_volt_info, sizeof(ptp_info_t)); 303 break; 304 case BOOT_TAG_EMI_INFO: 305 memcpy(&(g_boot_arg->emi_info), &(tags->u.emi_info), sizeof(emi_info_t)); 306 break; 307 case BOOT_TAG_IMGVER_INFO: 308 g_boot_arg->pl_imgver_status = tags->u.imgver_info.pl_imgver_status; 309 break; 310 case BOOT_TAG_MAX_CPUS: 311 g_boot_arg->max_cpus = tags->u.max_cpus.max_cpus; 312 break; 313 case BOOT_TAG_BAT_INFO: 314 g_boot_arg->boot_voltage = tags->u.bat_info.boot_voltage; 315 g_boot_arg->shutdown_time= tags->u.bat_info.shutdown_time; 316 break; 317 //#ifdef OPLUS_FEATURE_OEM_OCDT 318 case BOOT_TAG_OPLUSPROJECT_INFO: 319 g_boot_arg->nProject = tags->u.oplusproject_info.nProject; 320 g_boot_arg->nModem = tags->u.oplusproject_info.nModem; 321 g_boot_arg->nOperator = tags->u.oplusproject_info.nOperator; 322 g_boot_arg->nPCBVersion = tags->u.oplusproject_info.nPCBVersion; 323 g_boot_arg->nDownloadStatus =tags->u.oplusproject_info.nDownloadStatus; 324 g_boot_arg->nENGVersion = tags->u.oplusproject_info.nENGVersion; 325 g_boot_arg->isConfidential =tags->u.oplusproject_info.isConfidential; 326 break; 327 //#endif OPLUS_FEATURE_OEM_OCDT 328 case BOOT_TAG_RAM_CONSOLE_INFO: 329 g_boot_arg->ram_console_sram_addr = tags->u.ram_console_info.sram_addr; 330 g_boot_arg->ram_console_sram_size = tags->u.ram_console_info.sram_size; 331 g_boot_arg->ram_console_def_type = tags->u.ram_console_info.def_type; 332 g_boot_arg->ram_console_memory_info_offset = tags->u.ram_console_info.memory_info_offset; 333 break; 334 case BOOT_TAG_CHR_INFO: 335 g_boot_arg->charger_type = tags->u.chr_info.charger_type; 336 break; 337 #if WITH_GZ_MD_SHAREMEM 338 case BOOT_TAG_GZ_PARAM: 339 g_boot_arg->gz_md_shm_pa = tags->u.gz_param.modemMteeShareMemPA; 340 g_boot_arg->gz_md_shm_sz = tags->u.gz_param.modemMteeShareMemSize; 341 break; 342 #endif 343 case BOOT_TAG_SOC_ID: 344 memcpy(g_boot_arg->socid, tags->u.socid.id, SOC_ID_LEN); 345 break; 346 //#ifdef OPLUS_FEATURE_OEM_OCDT 347 case BOOT_TAG_OPLUSCDT_INFO: 348 g_boot_arg->nVersion = tags->u.opluscdt_info.nVersion; 349 g_boot_arg->nProject_newcdt = tags->u.opluscdt_info.nProject; 350 g_boot_arg->nDtsi = tags->u.opluscdt_info.nDtsi; 351 g_boot_arg->nAudio = tags->u.opluscdt_info.nAudio; 352 for (i = 0; i < FEATURE_COUNT; i++) { 353 g_boot_arg->nFeature[i] = tags->u.opluscdt_info.nFeature[i]; 354 } 355 g_boot_arg->newcdt = tags->u.opluscdt_info.newcdt; 356 g_boot_arg->nDownloadStatus_newcdt =tags->u.opluscdt_info.nDownloadStatus; 357 g_boot_arg->eng_version = tags->u.opluscdt_info.eng_version; 358 g_boot_arg->is_confidential = tags->u.opluscdt_info.is_confidential; 359 break; 360 //#endif OPLUS_FEATURE_OEM_OCDT 361 case BOOT_TAG_ROM_INFO: 362 m_sec_usb_dl = tags->u.rom_info.m_sec_usb_dl; 363 m_sec_boot = tags->u.rom_info.m_sec_boot; 364 m_seccfg_ac_en = tags->u.rom_info.m_seccfg_ac_en; 365 break; 366 default: 367 break; 368 } 369 bootarg_size += tags->hdr.size; 370 } 371 } 372 fpga_copy_boot_argument(g_boot_arg); 373 374 g_nr_bank = g_boot_arg->dram_rank_num; 375 376 if (g_nr_bank == 0 || g_nr_bank > MAX_NR_BANK) { 377 g_dram_init_ret = -1; 378 //dprintf(CRITICAL, "[LK ERROR] DRAM bank number is not correct!!!"); 379 //while (1) ; 380 return -1; 381 } 382 383 return 0; 384 } 385 386 unsigned int platform_get_bootarg_addr(void) 387 { 388 return bootarg_addr; 389 } 390 391 unsigned int platform_get_bootarg_size(void) 392 { 393 return bootarg_size; 394 } 395 396 /******************************************************* 397 * Routine: memory_size 398 * Description: return DRAM size to LCM driver 399 ******************************************************/ 400 u32 ddr_enable_4gb(void) 401 { 402 u32 status; 403 #define INFRA_MISC (INFRACFG_AO_BASE + 0x0F00) 404 #define INFRA_4GB_EN (1 << 13) 405 #define PERI_MISC (PERICFG_BASE + 0x0208) 406 #define PERI_4GB_EN (1 << 15) 407 408 status = ((DRV_Reg32(INFRA_MISC) & INFRA_4GB_EN) && (DRV_Reg32(PERI_MISC) & PERI_4GB_EN)) ? 1 : 0; 409 dprintf(CRITICAL, "%s() status=%u\n", __func__, status); 410 411 return status; 412 } 413 414 u64 physical_memory_size(void) 415 { 416 int i; 417 unsigned long long size = 0; 418 419 for (i = 0; i < (int)(g_boot_arg->orig_dram_info.rank_num); i++) { 420 size += g_boot_arg->orig_dram_info.rank_info[i].size; 421 } 422 423 return size; 424 } 425 426 u32 memory_size(void) 427 { 428 unsigned long long size = physical_memory_size(); 429 430 while (((unsigned long long)DRAM_PHY_ADDR + size) > 0x100000000ULL) { 431 size -= (unsigned long long)(1024*1024*1024); 432 } 433 434 return (unsigned int)size; 435 } 436 437 void sw_env() 438 { 439 //#ifdef OPLUS_BUG_STABILITY 440 /* Fuchun.Liao@BSP.CHG.Basic 2019/11/11 add for new cdt download info */ 441 u32 nDownloadStatus = 0; 442 //#endif /* OPLUS_BUG_STABILITY */ 443 #ifdef LK_DL_CHECK 444 #if defined(MTK_EMMC_SUPPORT) || defined(MTK_UFS_SUPPORT) 445 int dl_status = 0; 446 dl_status = mmc_get_dl_info(); 447 dprintf(INFO, "mt65xx_sw_env--dl_status: %d\n", dl_status); 448 if (dl_status != 0) { 449 video_printf("=> TOOL DL image Fail!\n"); 450 dprintf(CRITICAL, "TOOL DL image Fail\n"); 451 #ifdef LK_DL_CHECK_BLOCK_LEVEL 452 dprintf(CRITICAL, "uboot is blocking by dl info\n"); 453 while (1) ; 454 #endif 455 } 456 #endif 457 #endif 458 459 460 //#ifdef OPLUS_BUG_STABILITY 461 /* MingQiang.Guo@PSW.BSP.bootloader.bootflow, 2017/11/18, Add for check download over flag*/ 462 if (is_new_cdt()) { 463 nDownloadStatus = g_boot_arg->nDownloadStatus_newcdt; 464 } else { 465 nDownloadStatus = g_boot_arg->nDownloadStatus; 466 } 467 if (nDownloadStatus == BOOT_TAG_DOWNLOAD_OVER) { 468 dprintf(CRITICAL, "=> [oppo]Tool Download ok! 0x%x\n",g_boot_arg->nDownloadStatus); 469 } else if (nDownloadStatus == BOOT_TAG_DOWNLOAD_FAIL){ 470 video_printf("=> Download not completed! Please press volume+ and power key 10s to power off.\ 471 Then download again. Otherwise will block here 60S until shutdown automatically.\ 472 error code: 0x%x\n", nDownloadStatus); 473 dprintf(CRITICAL, "=> Download not completed! Please press volume+ and power key 10s to power off.\ 474 Then download again. Otherwise will block here 60S until shutdown automatically.\ 475 error code: 0x%x\n", nDownloadStatus); 476 mtk_wdt_disable(); 477 mdelay(60000); 478 mt_power_off(); 479 } 480 //#endif/*OPLUS_BUG_STABILITY*/ 481 482 #ifndef MACH_FPGA_NO_DISPLAY 483 #ifndef USER_BUILD 484 switch (g_boot_mode) { 485 case META_BOOT: 486 video_printf(" => META MODE\n"); 487 break; 488 case FACTORY_BOOT: 489 video_printf(" => FACTORY MODE\n"); 490 break; 491 case RECOVERY_BOOT: 492 video_printf(" => RECOVERY MODE\n"); 493 break; 494 case SW_REBOOT: 495 //video_printf(" => SW RESET\n"); 496 break; 497 case NORMAL_BOOT: 498 //if(g_boot_arg->boot_reason != BR_RTC && get_env("hibboot") != NULL && atoi(get_env("hibboot")) == 1) 499 if (get_env("hibboot") != NULL && atoi(get_env("hibboot")) == 1) 500 video_printf(" => HIBERNATION BOOT\n"); 501 else 502 video_printf(" => NORMAL BOOT\n"); 503 break; 504 case ADVMETA_BOOT: 505 video_printf(" => ADVANCED META MODE\n"); 506 break; 507 case ATE_FACTORY_BOOT: 508 video_printf(" => ATE FACTORY MODE\n"); 509 break; 510 #ifdef MTK_KERNEL_POWER_OFF_CHARGING 511 case KERNEL_POWER_OFF_CHARGING_BOOT: 512 video_printf(" => POWER OFF CHARGING MODE\n"); 513 break; 514 case LOW_POWER_OFF_CHARGING_BOOT: 515 video_printf(" => LOW POWER OFF CHARGING MODE\n"); 516 break; 517 #endif 518 case ALARM_BOOT: 519 video_printf(" => ALARM BOOT\n"); 520 break; 521 case FASTBOOT: 522 video_printf(" => FASTBOOT mode...\n"); 523 break; 524 default: 525 video_printf(" => UNKNOWN BOOT\n"); 526 } 527 return; 528 #endif 529 530 #ifdef USER_BUILD 531 /* it's ok to display META MODE since it already verfied by preloader */ 532 if (g_boot_mode == META_BOOT) 533 video_printf(" => META MODE\n"); 534 if (g_boot_mode == FASTBOOT) 535 video_printf(" => FASTBOOT mode...\n"); 536 #ifdef OPLUS_FEATURE_OEM_BOOT_MODE 537 if (g_boot_mode == FACTORY_BOOT) 538 video_printf(" => FACTORY mode...\n"); 539 if (g_boot_mode == RECOVERY_BOOT) 540 video_printf(" => RECOVERY mode...\n"); 541 #endif 542 return; 543 #endif 544 #endif /* MACH_FPGA_NO_DISPLAY */ 545 } 546 547 extern uint64_t ld_tt_l1[4]; 548 void platform_init_mmu(void) 549 { 550 /* configure available RAM banks */ 551 dram_init(); 552 /* Long-descriptor translation with lpae enable */ 553 arm_mmu_lpae_init(); 554 555 struct mmu_initial_mapping *m = mmu_initial_mappings; 556 557 for (uint i = 0; i < countof(mmu_initial_mappings); i++, m++) { 558 arch_mmu_map(m->phys, m->virt, m->flags, m->size); 559 } 560 561 arch_enable_mmu(); //enable mmu after setup page table to avoid cpu prefetch which may bring on emi violation 562 } 563 564 565 /****************************************************************************** 566 ******************************************************************************/ 567 void init_storage(void) 568 { 569 PROFILING_START("NAND/EMMC init"); 570 571 #if defined(MTK_EMMC_SUPPORT) 572 mmc_legacy_init(1); 573 #elif defined(MTK_UFS_SUPPORT) 574 ufs_lk_init(); 575 #else 576 #ifndef MACH_FPGA 577 nand_init(); 578 nand_driver_test(); 579 #endif // MACH_FPGA 580 #endif // MTK_EMMC_SUPPORT 581 582 #if defined(MTK_EMMC_SUPPORT) || defined(MTK_UFS_SUPPORT) 583 init_rpmb_sharemem(); 584 #endif 585 586 PROFILING_END(); /* NAND/EMMC init */ 587 } 588 589 590 /****************************************************************************** 591 ******************************************************************************/ 592 void platform_early_init(void) 593 { 594 PROFILING_START("platform_early_init"); 595 #ifdef MTK_LK_REGISTER_WDT 596 lk_register_wdt_callback(); 597 #endif 598 599 /* initialize the uart */ 600 uart_init_early(); 601 602 PROFILING_START("Devinfo Init"); 603 init_devinfo_data(); 604 PROFILING_END(); 605 606 platform_init_interrupts(); 607 #ifndef MTK_POL_DEPRECATED 608 #ifdef MTK_SYSIRQ_INIT_LK 609 mt_irq_sysirq_init(); 610 #endif 611 #endif 612 platform_early_init_timer(); 613 614 #if !defined(USE_DTB_NO_DWS) && !defined(MACH_FPGA) 615 mt_gpio_set_default(); 616 #endif // !defined(USE_DTB_NO_DWS) && !defined(MACH_FPGA) 617 618 dprintf(SPEW, "bootarg_addr: 0x%x, bootarg_size: 0x%x\n", platform_get_bootarg_addr(), platform_get_bootarg_size()); 619 620 if (g_dram_init_ret < 0) { 621 dprintf(CRITICAL, "[LK ERROR] DRAM bank number is not correct!!!\n"); 622 while (1) ; 623 } 624 625 //i2c_v1_init(); 626 PROFILING_START("WDT Init"); 627 mtk_wdt_init(); 628 PROFILING_END(); 629 630 //i2c init 631 i2c_hw_init(); 632 633 #ifdef MACH_FPGA 634 mtk_timer_init(); // GPT4 will be initialized at PL after 635 mtk_wdt_disable(); // WDT will be triggered when uncompressing linux image on FPGA 636 #endif 637 pwrap_init_lk(); 638 639 #if !defined(MACH_FPGA) && !defined(NO_PMIC) 640 PROFILING_START("pmic_init"); 641 pmic_init(); 642 PROFILING_END(); 643 #endif // !defined(MACH_FPGA) && !defined(NO_PMIC) 644 PROFILING_END(); /* platform_early_init */ 645 } 646 647 extern void mt65xx_bat_init(void); 648 extern bool mtk_bat_allow_backlight_enable(void); 649 #if defined (MTK_KERNEL_POWER_OFF_CHARGING) 650 651 int kernel_charging_boot(void) 652 { 653 if ((g_boot_mode == KERNEL_POWER_OFF_CHARGING_BOOT || g_boot_mode == LOW_POWER_OFF_CHARGING_BOOT) && upmu_is_chr_det() == KAL_TRUE) { 654 dprintf(INFO,"[%s] Kernel Power Off Charging with Charger/Usb \n", __func__); 655 return 1; 656 } else if ((g_boot_mode == KERNEL_POWER_OFF_CHARGING_BOOT || g_boot_mode == LOW_POWER_OFF_CHARGING_BOOT) && upmu_is_chr_det() == KAL_FALSE) { 657 dprintf(INFO,"[%s] Kernel Power Off Charging without Charger/Usb \n", __func__); 658 return -1; 659 } else 660 return 0; 661 } 662 #endif 663 664 static void lk_vb_init(void) 665 { 666 #ifdef MTK_SECURITY_SW_SUPPORT 667 u64 pl_start_addr = 0; 668 #ifdef MTK_VER_SIMPLE_TEST 669 u32 ret = 0; 670 ret = sec_mtk_internal_ver_test(MTK_VER_SIMPLE_TEST); 671 if (ret) 672 assert(0); 673 #endif 674 675 #ifdef MTK_OTP_FRAMEWORK_V2 676 enable_anti_rollback_v2_framework(); 677 #endif 678 679 plinfo_get_brom_header_block_size(&pl_start_addr); 680 681 PROFILING_START("Security init"); 682 /* initialize security library */ 683 sec_func_init(pl_start_addr); 684 seclib_set_oemkey(g_oemkey, OEM_PUBK_SZ); 685 PROFILING_END(); 686 #endif 687 } 688 689 static void lk_vb_vfy_logo(void) 690 { 691 #ifdef MTK_SECURITY_SW_SUPPORT 692 /* bypass logo vfy in fast meta mode */ 693 if(g_boot_mode == META_BOOT) 694 return; 695 696 PROFILING_START("logo verify"); 697 /*Verify logo before use it*/ 698 if (0 != img_auth_stor("logo", "logo", 0x0)) 699 assert(0); 700 701 PROFILING_END(); 702 #endif 703 } 704 705 //#ifdef OPLUS_FEATURE_SECURITY_COMMON 706 int32_t mtk_set_boot_info_to_rpmb() 707 { 708 int32_t ret = 0; 709 uint32_t sboot_state = 1; 710 int32_t lock_state = 1; 711 int32_t isunlocked = 0; 712 713 ret = get_sboot_state(&sboot_state); 714 if (ret) { 715 sboot_state = 1; //set default:secureboot on:1; off:0 716 } 717 718 if (sboot_state == 1) { 719 cmdline_append("mtkboot.sbootstate=on"); 720 } 721 722 ret = sec_query_device_lock(&lock_state); 723 if (ret) { 724 lock_state = 1; //set default:device lock:1 ; unlock:0 725 } 726 727 if (lock_state == 0) 728 isunlocked = 1; 729 730 dprintf(CRITICAL, "sboot_state is %d, lock_state is %d, isunlocked is %d \n", sboot_state, lock_state, isunlocked); 731 ret = set_boot_info_to_rpmb((bool)sboot_state, isunlocked); 732 if (ret) { 733 dprintf(CRITICAL, "%s set boot info to rpmb fail !!!\n", __func__); 734 } 735 736 return ret; 737 } 738 //#endif /* OPLUS_FEATURE_SECURITY_COMMON */ 739 740 void platform_init(void) 741 { 742 bool backlight_on = false; 743 int logo_size; 744 //like@BSP.Storage.UFS, 2022/11/25 add for emmc/UFS compatible 745 part_dev_t *dev; 746 747 #ifdef OPLUS_FEATURE_CHG_BASIC 748 int boot_vbat; 749 int chr_vol = 0; 750 751 /* 5 doesn't mean anything in this function */ 752 boot_vbat = get_bat_volt(5); 753 #endif /*OPLUS_FEATURE_CHG_BASIC*/ 754 755 PROFILING_START("platform_init"); 756 dprintf(CRITICAL, "platform_init()\n"); 757 758 init_storage(); 759 lk_vb_init(); 760 //like@BSP.Storage.UFS, 2022/11/25 add for emmc/ufs compatible 761 dev = mt_part_get_device(); 762 763 extern void dummy_ap_entry(void)__attribute__((weak)); /* This is empty function for normal load */ 764 if (dummy_ap_entry) 765 dummy_ap_entry(); 766 767 #ifdef MTK_AB_OTA_UPDATER 768 /* get A/B system parameter before load dtb from boot image */ 769 get_AB_OTA_param(); 770 #endif 771 /* 772 * RSC initialize. It must be done before load device tree. 773 * rsc_init will ectract DTBO index, which will be used in device 774 * tree overlay, from PARA partition 775 */ 776 rsc_init(); 777 778 /* The device tree should be loaded as early as possible. */ 779 load_device_tree(); 780 781 #if defined(USE_DTB_NO_DWS) && !defined(MACH_FPGA) 782 mt_gpio_set_default(); 783 #endif // defined(USE_DTB_NO_DWS) && !defined(MACH_FPGA) 784 bdg_tx_pull_6382_reset_pin(); 785 786 clk_buf_disp_ctrl(true); 787 /* spi slave driver probe */ 788 spi_slave_probe(); 789 #ifdef MT6768_REF_DEV 790 mdelay(5); 791 bdg_tx_pull_6382_reset_pin(); 792 #endif 793 794 #ifdef OPLUS_FEATURE_CHG_BASIC 795 struct mtk_charger_info *primary_mchr = NULL; 796 mtk_charger_init(); 797 primary_mchr = mtk_charger_get_by_name("primary_charger"); 798 if (!primary_mchr) { 799 dprintf(CRITICAL, "%s: get primary charger failed\n", __func__); 800 } else { 801 dprintf(CRITICAL, "%s: get primary charger OK\n", __func__); 802 mtk_charger_set_ichg(primary_mchr, 300); 803 mtk_charger_set_aicr(primary_mchr, 1000); 804 mtk_charger_enable_charging(primary_mchr, KAL_TRUE); 805 } 806 #endif /*OPLUS_FEATURE_CHG_BASIC*/ 807 808 #ifndef MACH_FPGA 809 PROFILING_START("led init"); 810 leds_init(); 811 PROFILING_END(); 812 #endif // MACH_FPGA 813 814 #ifdef MTK_KERNEL_POWER_OFF_CHARGING 815 if ((g_boot_arg->boot_reason == BR_USB) && (upmu_is_chr_det() == KAL_FALSE)) { 816 dprintf(INFO, "[%s] Unplugged Charger/Usb between Pre-loader and Uboot in Kernel Charging Mode, Power Off \n", __func__); 817 mt_power_off(); 818 } 819 #endif // MTK_KERNEL_POWER_OFF_CHARGING 820 821 #ifndef MACH_FPGA_NO_DISPLAY 822 PROFILING_START("ENV init"); 823 env_init(); 824 print_env(); 825 PROFILING_END(); 826 if (g_boot_arg->boot_mode == NORMAL_BOOT) 827 { 828 if (dev->blkdev->type == BOOTDEV_SDMMC) 829 cmd_oem_getemmcinfo(); 830 #ifdef MTK_UFS_SUPPORT 831 else if(dev->blkdev->type == BOOTDEV_UFS) 832 { 833 if(!cmd_oem_get_ufs_info()) 834 dprintf(CRITICAL, "fail to get ufs info\n"); 835 } 836 #endif 837 } 838 if (dev->blkdev->type == BOOTDEV_SDMMC) 839 { 840 int ret = 0; 841 unsigned long vendor_argu = 0; 842 unsigned char *fw_buff_addr = NULL; 843 struct mmc_card *mmc_card; 844 mmc_card=mmc_get_card(0); 845 if (mmc_card->cid.manfid == MICRON_VENDOR_MANFID) 846 { 847 cmdline_append("emmc_max_chunck_size=262144");//256kB 848 } 849 else 850 cmdline_append("emmc_max_chunck_size=4194304");//4MB 851 if (g_boot_arg->boot_mode == NORMAL_BOOT) 852 { 853 fw_buff_addr = malloc(512*1024);//szie for max FW length 854 if (fw_buff_addr) 855 { 856 if (mmc_card->cid.manfid == HYNIX_VENDOR_MANFID)//hynix specific 2D & 3D nand emcp 857 { 858 vendor_argu = HYNIX_FFU_ARG; 859 } 860 else if (mmc_card->cid.manfid == SUMSUNG_VENDOR_MANFID) 861 { 862 vendor_argu = SUMSUNG_FFU_ARG; 863 } 864 else if (mmc_card->cid.manfid == MICRON_VENDOR_MANFID)//micron specific emcp 865 { 866 vendor_argu = MICRON_FFU_ARG; // currentlly micron emcp is not in use 867 } 868 else if (mmc_card->cid.manfid == YMTC_VENDOR_MANFID)//micron specific emcp 869 { 870 dprintf(CRITICAL, "Emmc prod_name:%s\n", mmc_card->cid.prod_name); 871 if (!strcmp(mmc_card->cid.prod_name, "Y0S064") || !strcmp(mmc_card->cid.prod_name, "Y0S128") || !strcmp(mmc_card->cid.prod_name, "Y0S256") 872 || !strcmp(mmc_card->cid.prod_name, "Y1Y128") || !strcmp(mmc_card->cid.prod_name, "Y1Y256")) { 873 vendor_argu = YMTC_FFU_ARG_NEW; 874 } else { 875 vendor_argu = YMTC_FFU_ARG; 876 } 877 } 878 else if ((mmc_card->cid.manfid == FORESEE_VENDOR_MANFID) && (mmc_card->cid.bin == FORESEE_VENDOR_BIN)) 879 { 880 vendor_argu = FORESEE_FFU_ARG; 881 } 882 else if (mmc_card->cid.manfid == HG_VENDOR_MANFID) 883 { 884 vendor_argu = HG_FFU_ARG; 885 } 886 else if (mmc_card->cid.manfid == BIWIN_VENDOR_MANFID) 887 { 888 vendor_argu = BIWIN_FFU_ARG; 889 } 890 else 891 { 892 dprintf(CRITICAL, "Unknown manfid emcp.\n"); 893 } 894 dprintf(CRITICAL, "Emmc check upgrade start vendor_argu=0x%08x\n",vendor_argu); 895 if ((need_upgrade_emmc_fimware(0, fw_buff_addr) || need_upgrade_emmc_fimware(1024*1024, fw_buff_addr))) 896 { 897 dprintf(CRITICAL, "Start emmc firmware upgrade flow\n"); 898 ret = emmc_firmware_upgrade_flow(vendor_argu, fw_buff_addr); 899 dprintf(CRITICAL, "%s::Reboot device\n",__func__); 900 if(mtk_rgu_mode_check(MTK_WDT_NONRST2_BOOT_SILENCE)){ 901 mtk_rgu_mode_set(1,MTK_WDT_NONRST2_BOOT_SILENCE); 902 } 903 if(mtk_rgu_mode_check(MTK_WDT_NONRST2_BOOT_SAU)){ 904 mtk_rgu_mode_set(1,MTK_WDT_NONRST2_BOOT_SAU); 905 } 906 mmc_legacy_init(1); 907 mtk_arch_reset(1); 908 } 909 dprintf(CRITICAL, "Emmc check upgrade end\n"); 910 free(fw_buff_addr); 911 } 912 else 913 dprintf(CRITICAL, "malloc fail for emmc fw upgrade.\n"); 914 } 915 } 916 #ifdef MTK_UFS_SUPPORT 917 else if(dev->blkdev->type == BOOTDEV_UFS) 918 { 919 if (g_boot_arg->boot_mode == NORMAL_BOOT) 920 { 921 uint8_t *fw_buff_align; 922 unsigned char *fw_buff = malloc(FIRMWARE_LENGTH_MAX +BUF_ALIGN_8); 923 if(fw_buff) 924 { 925 fw_buff_align = UFS_PALIGN(fw_buff, BUF_ALIGN_8); 926 if (need_upgrade_ufs_firmware(fw_buff_align)) 927 { 928 dprintf(CRITICAL, "Start emmc firmware upgrade flow\n"); 929 if (ufs_firmware_update(fw_buff_align) == 0) 930 dprintf(CRITICAL, "ufs FW upgrade success.\n"); 931 dprintf(CRITICAL, "%s::Reboot device\n",__func__); 932 ufs_lk_init(); 933 mtk_arch_full_reset(); 934 } 935 } 936 else 937 dprintf(CRITICAL, "malloc fail for ufs fw upgrade.\n"); 938 free(fw_buff); 939 } 940 } 941 #endif 942 943 PROFILING_START("disp init"); 944 /* initialize the frame buffet information */ 945 g_fb_size = mt_disp_get_vram_size(); 946 g_fb_base = mblock_reserve_ext(&g_boot_arg->mblock_info, g_fb_size, 0x10000, 0x80000000, 0, "framebuffer"); 947 if (!g_fb_base) { 948 dprintf(CRITICAL, "reserve framebuffer failed\n"); 949 } 950 951 dprintf(CRITICAL, "FB base = 0x%x, FB size = 0x%x (%d)\n", g_fb_base, g_fb_size, g_fb_size); 952 953 #ifndef MACH_FPGA 954 #ifdef MTK_SMI_SUPPORT 955 /* write SMI non on-the-fly register before DISP init */ 956 smi_apply_register_setting(); 957 #endif 958 #endif 959 960 mt_disp_init((void *)g_fb_base); 961 PROFILING_END(); 962 963 PROFILING_START("vedio init"); 964 drv_video_init(); 965 PROFILING_END(); 966 #endif /* MACH_FPGA_NO_DISPLAY */ 967 968 /*for kpd pmic mode setting*/ 969 set_kpd_pmic_mode(); 970 971 #ifndef MACH_FPGA 972 PROFILING_START("boot mode select"); 973 974 #if !defined(NO_BOOT_MODE_SEL) 975 boot_mode_select(); 976 #endif 977 978 PROFILING_START("wdt_check_exception"); 979 wdt_check_exception(); 980 PROFILING_END(); 981 982 #ifdef MTK_USB2JTAG_SUPPORT 983 if (g_boot_mode != FASTBOOT) { 984 extern void usb2jtag_init(void); 985 usb2jtag_init(); 986 } 987 #endif 988 989 #ifdef MTK_AEE_PLATFORM_DEBUG_SUPPORT 990 /* init lastbus: MUST call after kedump (in boot_mode_select) */ 991 latch_lastbus_init(); 992 #endif 993 994 PROFILING_END(); /* boot mode select */ 995 #endif /*MACH_FPGA */ 996 997 lk_vb_vfy_logo(); 998 999 #ifdef OPLUS_FEATURE_CHG_BASIC 1000 if(g_boot_mode == OPPO_SAU_BOOT || g_boot_mode == SILENCE_BOOT){ 1001 dprintf(CRITICAL,"silence or sau boot do nothing\r\n"); 1002 //silence and sau boot do nothing 1003 } else { 1004 if (boot_vbat >= VIB_BOOT_THRESHOLD_MV) { 1005 platform_vib_timed_enable(VIB_DURATION); 1006 } else { 1007 dprintf(CRITICAL, "boot vbatt is lower than 3200mV, do not vibration0.\n"); 1008 } 1009 } 1010 #endif /* OPLUS_FEATURE_CHG_BASIC */ 1011 1012 #ifndef MACH_FPGA_NO_DISPLAY 1013 /* fast meta mode */ 1014 if(g_boot_mode != META_BOOT){ 1015 PROFILING_START("load_logo"); 1016 logo_size = mboot_common_load_logo((unsigned long)mt_get_logo_db_addr_pa(), "logo"); 1017 assert(logo_size <= LK_LOGO_MAX_SIZE); 1018 PROFILING_END(); 1019 } else 1020 /* Indicate logo lib that logo partition is not loaded */ 1021 enable_logo(0); 1022 #endif // MACH_FPGA_NO_DISPLAY 1023 1024 /*Show download logo & message on screen */ 1025 if (g_boot_arg->boot_mode == DOWNLOAD_BOOT) { 1026 dprintf(CRITICAL, "[LK] boot mode is DOWNLOAD_BOOT\n"); 1027 1028 #ifndef MACH_FPGA_NO_DISPLAY 1029 PROFILING_START("show logo"); 1030 mt_disp_show_boot_logo(); 1031 PROFILING_END(); 1032 #endif 1033 video_printf(" => Downloading...\n"); 1034 dprintf(CRITICAL, "enable backlight after show bootlogo! \n"); 1035 #ifndef MACH_FPGA 1036 PROFILING_START("backlight"); 1037 mt65xx_backlight_on(); 1038 PROFILING_END(); 1039 #endif 1040 #ifndef MACH_FPGA_NO_DISPLAY 1041 /* pwm need display sof */ 1042 PROFILING_START("disp update"); 1043 mt_disp_update(0, 0, CFG_DISPLAY_WIDTH, CFG_DISPLAY_HEIGHT); 1044 PROFILING_END(); 1045 #endif 1046 logo_lk_t = ((unsigned int)get_timer(boot_time)); 1047 PROFILING_START("disable wdt, l2, cache, mmu"); 1048 mtk_wdt_disable(); //Disable wdt before jump to DA 1049 platform_uninit(); 1050 #ifdef HAVE_CACHE_PL310 1051 l2_disable(); 1052 #endif 1053 arch_disable_cache(UCACHE); 1054 arch_disable_mmu(); 1055 #ifdef ENABLE_L2_SHARING 1056 config_shared_SRAM_size(); 1057 #endif 1058 PROFILING_END(); 1059 jump_da(g_boot_arg->da_info.addr, g_boot_arg->da_info.arg1, g_boot_arg->da_info.arg2); 1060 } 1061 #ifdef MTK_KERNEL_POWER_OFF_CHARGING 1062 else if (g_boot_mode != META_BOOT && 1063 g_boot_mode != ALARM_BOOT && 1064 g_boot_mode != FASTBOOT && 1065 g_boot_mode != KERNEL_POWER_OFF_CHARGING_BOOT && 1066 g_boot_mode != LOW_POWER_OFF_CHARGING_BOOT && 1067 mtk_bat_allow_backlight_enable()) { 1068 #ifndef MACH_FPGA_NO_DISPLAY 1069 #ifdef OPLUS_FEATURE_CHG_BASIC 1070 boot_vbat = get_bat_volt(5); 1071 //if(boot_vbat > BATTERY_LOWVOL_THRESOLD) { 1072 PROFILING_START("show logo"); 1073 mt_disp_show_boot_logo(); 1074 PROFILING_END(); 1075 //} 1076 #endif /* OPLUS_FEATURE_CHG_BASIC */ 1077 #endif // MACH_FPGA_NO_DISPLAY 1078 #ifndef MACH_FPGA 1079 PROFILING_START("backlight"); 1080 mt65xx_backlight_on(); 1081 PROFILING_END(); /* backlight */ 1082 #endif 1083 #ifndef MACH_FPGA_NO_DISPLAY 1084 /* pwm need display sof */ 1085 PROFILING_START("disp update"); 1086 mt_disp_update(0, 0, CFG_DISPLAY_WIDTH, CFG_DISPLAY_HEIGHT); 1087 PROFILING_END(); 1088 #endif 1089 backlight_on = true; 1090 dprintf(INFO, "backlight enabled before battery init\n"); 1091 logo_lk_t = ((unsigned int)get_timer(boot_time)); 1092 } 1093 #endif // MTK_KERNEL_POWER_OFF_CHARGING 1094 1095 PROFILING_START("battery init"); 1096 #ifndef MACH_FPGA 1097 #if !defined(NO_PLL_TURN_OFF) 1098 mt_pll_turn_off(); 1099 #endif // !defined(NO_PLL_TURN_OFF) 1100 #if !defined(NO_DCM) 1101 if (mt_dcm_init()) 1102 dprintf(CRITICAL, "mt_dcm_init fail\n"); 1103 #endif // !defined(NO_DCM) 1104 1105 #if !defined(NO_BAT_INIT) 1106 #ifdef MTK_CHARGER_NEW_ARCH 1107 PROFILING_START("charger init"); 1108 mtk_charger_init(); 1109 PROFILING_END(); /* charger init */ 1110 1111 PROFILING_START("DLPT init"); 1112 pmic_dlpt_init(); 1113 PROFILING_END(); /* dlpt init */ 1114 1115 PROFILING_START("check sw_ocv"); 1116 check_sw_ocv(); 1117 PROFILING_END(); /* battery check sw_ocv */ 1118 1119 PROFILING_START("charger start"); 1120 mtk_charger_start(); 1121 PROFILING_END(); /* charger start */ 1122 1123 PROFILING_START(" DLPT get imix"); 1124 get_dlpt_imix_r(); 1125 PROFILING_END(); /* DLPT get imix */ 1126 1127 #else 1128 mt65xx_bat_init(); 1129 #endif // MTK_CHARGER_NEW_ARCH 1130 #endif // !defined(NO_BAT_INIT) 1131 #endif // MACH_FPGA 1132 PROFILING_END(); /* battery init */ 1133 1134 #ifndef CFG_POWER_CHARGING 1135 PROFILING_START("RTC boot check Init"); 1136 /* NOTE: if define CFG_POWER_CHARGING, will rtc_boot_check() in mt65xx_bat_init() */ 1137 rtc_boot_check(false); 1138 PROFILING_END(); 1139 #endif // CFG_POWER_CHARGING 1140 1141 #ifdef MTK_KERNEL_POWER_OFF_CHARGING 1142 if (kernel_charging_boot() == 1) { 1143 PROFILING_START("show logo"); 1144 #ifdef MTK_BATLOWV_NO_PANEL_ON_EARLY 1145 CHARGER_TYPE CHR_Type_num = CHARGER_UNKNOWN; 1146 CHR_Type_num = hw_charging_get_charger_type(); 1147 if ((g_boot_mode != LOW_POWER_OFF_CHARGING_BOOT) || 1148 ((CHR_Type_num != STANDARD_HOST) && (CHR_Type_num != NONSTANDARD_CHARGER))) { 1149 #endif // MTK_BATLOWV_NO_PANEL_ON_EARLY 1150 mt_disp_power(TRUE); 1151 #ifndef OPLUS_FEATURE_CHG_BASIC 1152 #ifndef MACH_FPGA_NO_DISPLAY 1153 mt_disp_show_low_battery(); 1154 #endif 1155 mt65xx_leds_brightness_set(6, 110); 1156 #endif /*OPLUS_FEATURE_CHG_BASIC*/ 1157 1158 #ifndef MACH_FPGA_NO_DISPLAY 1159 /* pwm need display sof */ 1160 PROFILING_START("display update"); 1161 mt_disp_update(0, 0, CFG_DISPLAY_WIDTH, CFG_DISPLAY_HEIGHT); 1162 PROFILING_END(); 1163 #endif 1164 backlight_on = true; 1165 #ifdef MTK_BATLOWV_NO_PANEL_ON_EARLY 1166 } 1167 #endif 1168 PROFILING_END(); 1169 } 1170 #endif // MTK_KERNEL_POWER_OFF_CHARGING 1171 1172 #ifdef MTK_BATLOWV_NO_PANEL_ON_EARLY 1173 if (!is_low_battery(0)) { 1174 #endif 1175 /* 1176 * Update LCM with framebuffer before 1177 * turning on backlight to avoid LCM noise if there is 1178 * no any logo showed on screen before. 1179 */ 1180 if (!backlight_on) { 1181 logo_lk_t = ((unsigned int)get_timer(boot_time)); 1182 #ifndef MACH_FPGA_NO_DISPLAY 1183 PROFILING_START("display update"); 1184 mt_disp_update(0, 0, CFG_DISPLAY_WIDTH, CFG_DISPLAY_HEIGHT); 1185 PROFILING_END(); 1186 #endif 1187 #ifndef MACH_FPGA 1188 PROFILING_START("backlight"); 1189 mt65xx_backlight_on(); 1190 PROFILING_END(); /* backlight */ 1191 #endif 1192 } 1193 #ifdef MTK_BATLOWV_NO_PANEL_ON_EARLY 1194 } 1195 #endif 1196 //#ifdef OPLUS_FEATURE_SECURITY_COMMON 1197 //#Shupeng.Zhou@BSP.Secure.Basic, 2020/11/18, add for FBE key aquire permission 1198 mtk_set_boot_info_to_rpmb(); 1199 //#endif /* OPLUS_FEATURE_SECURITY_COMMON */ 1200 #ifndef MACH_FPGA 1201 PROFILING_START("sw_env"); 1202 sw_env(); 1203 PROFILING_END(); 1204 #endif 1205 PROFILING_END(); /* platform_init */ 1206 } 1207 1208 void platform_uninit(void) 1209 { 1210 #ifndef MACH_FPGA 1211 leds_deinit(); 1212 platform_clear_all_on_mux(); 1213 #endif 1214 platform_deinit_interrupts(); 1215 return; 1216 } 1217 1218 #ifdef ENABLE_L2_SHARING 1219 #define ADDR_CA7L_CACHE_CONFIG_MP(x) (CA7MCUCFG_BASE + 0x200 * x) 1220 #define L2C_SIZE_CFG_OFFSET 8 1221 #define L2C_SHARE_EN_OFFSET 12 1222 /* 4'b1111: 2048KB(not support) 1223 * 4'b0111: 1024KB(not support) 1224 * 4'b0011: 512KB 1225 * 4'b0001: 256KB 1226 * 4'b0000: 128KB (not support) 1227 */ 1228 1229 int is_l2_need_config(void) 1230 { 1231 volatile unsigned int cache_cfg, addr; 1232 1233 addr = ADDR_CA7L_CACHE_CONFIG_MP(0); 1234 cache_cfg = DRV_Reg32(addr); 1235 cache_cfg = cache_cfg >> L2C_SIZE_CFG_OFFSET; 1236 1237 /* only read 256KB need to be config.*/ 1238 if ((cache_cfg &(0x7)) == 0x1) { 1239 return 1; 1240 } 1241 return 0; 1242 } 1243 1244 void cluster_l2_share_enable(int cluster) 1245 { 1246 volatile unsigned int cache_cfg, addr; 1247 1248 addr = ADDR_CA7L_CACHE_CONFIG_MP(cluster); 1249 /* set L2C size to 256KB */ 1250 cache_cfg = DRV_Reg32(addr); 1251 cache_cfg &= (~0x7) << L2C_SIZE_CFG_OFFSET; 1252 cache_cfg |= 0x1 << L2C_SIZE_CFG_OFFSET; 1253 1254 /* enable L2C_share_en. Sram only for other to use*/ 1255 cache_cfg |= (0x1 << L2C_SHARE_EN_OFFSET); 1256 DRV_WriteReg32(addr, cache_cfg); 1257 } 1258 1259 void cluster_l2_share_disable(int cluster) 1260 { 1261 volatile unsigned int cache_cfg, addr; 1262 1263 addr = ADDR_CA7L_CACHE_CONFIG_MP(cluster); 1264 /* set L2C size to 512KB */ 1265 cache_cfg = DRV_Reg32(addr); 1266 cache_cfg &= (~0x7) << L2C_SIZE_CFG_OFFSET; 1267 cache_cfg |= 0x3 << L2C_SIZE_CFG_OFFSET; 1268 DRV_WriteReg32(addr, cache_cfg); 1269 1270 /* disable L2C_share_en. Sram only for cpu to use*/ 1271 cache_cfg &= ~(0x1 << L2C_SHARE_EN_OFFSET); 1272 DRV_WriteReg32(addr, cache_cfg); 1273 } 1274 1275 /* config L2 cache and sram to its size */ 1276 void config_L2_size(void) 1277 { 1278 int cluster; 1279 1280 if (is_l2_need_config()) { 1281 /* 1282 * Becuase mcu config is protected. 1283 * only can write in secutity mode 1284 */ 1285 1286 if (dev_info_nr_cpu() == 6) { 1287 cluster_l2_share_disable(0); 1288 cluster_l2_share_enable(1); 1289 } 1290 1291 else { 1292 for (cluster = 0; cluster < 2; cluster++) { 1293 cluster_l2_share_disable(cluster); 1294 } 1295 } 1296 } 1297 } 1298 1299 /* config SRAM back from L2 cache for DA relocation */ 1300 void config_shared_SRAM_size(void) 1301 { 1302 int cluster; 1303 1304 if (is_l2_need_config()) { 1305 /* 1306 * Becuase mcu config is protected. 1307 * only can write in secutity mode 1308 */ 1309 1310 for (cluster = 0; cluster < 2; cluster++) { 1311 cluster_l2_share_enable(cluster); 1312 } 1313 } 1314 } 1315 #endif 1316 1317 1318 void platform_sec_post_init(void) 1319 { 1320 unsigned int ret = 0; 1321 ret = crypto_hw_engine_disable(); 1322 if (ret) { 1323 dprintf(CRITICAL, "[SEC] crypto engine HW disable fail\n"); 1324 } 1325 /* Lock Device APC in LK */ 1326 dprintf(CRITICAL, "[DEVAPC] sec_post_init\n"); 1327 1328 #if DEVAPC_TURN_ON 1329 dprintf(CRITICAL, "[DEVAPC] platform_sec_post_init - SMC call to ATF from LK\n"); 1330 #ifdef MTK_SMC_ID_MGMT 1331 mt_secure_call(MTK_SIP_LK_DAPC_INIT, 0, 0, 0, 0); 1332 #else 1333 mt_secure_call(0x82000101, 0, 0, 0); 1334 #endif 1335 #endif 1336 1337 } 1338 1339 u32 get_devinfo_with_index(u32 index) 1340 { 1341 return internal_get_devinfo_with_index(index); 1342 } 1343 1344 int platform_skip_hibernation(void) 1345 { 1346 switch (g_boot_arg->boot_reason) { 1347 #if 0 // let schedule power on to go hiberantion bootup process 1348 case BR_RTC: 1349 #endif 1350 case BR_WDT: 1351 case BR_WDT_BY_PASS_PWK: 1352 case BR_WDT_SW: 1353 case BR_WDT_HW: 1354 return 1; 1355 } 1356 1357 return 0; 1358 } 1359 1360 int is_meta_log_disable(void) 1361 { 1362 return g_boot_arg->meta_log_disable; 1363 } 1364 1365 served by {OpenGrok Last Index Update: Thu Aug 07 23:03:58 CST 2025这里面有哪个文件会修改boot_mode
11-28
评论
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值