数字秒表的设计

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最新推荐文章于 2024-08-30 22:43:24 发布

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文章标签： fpga开发

本文链接：https://blog.youkuaiyun.com/qq_71663825/article/details/137572550

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实验要求：今需设计一个计时范围为0.01s～1h的数字秒表，首先需要获得一个比较精确的计时基准信号，这里是周期为1/100s的计时脉冲。其次，除了对每一计数器需设置清零信号输入外，还需为六个计数器设置时钟使能信号，即计时允许信号，以便作为秒表的计时起、停控制开关。因此数字秒表可由一个分频器、四个十进制计数器(1/100 s、1/10 s、1 s、1 min)以及两个六进制计数器(10 s、10 min)组成，

6个计数器中的每一计数器的4位输出，通过外设的BCD译码器输出显示。图1中，6个4位二进制计数器输出的最小显示值分别为：DOUT3.0]→1/100s、DOUT[7.4]→1/10s、DOUT[11.8]→1s、DOUT[15..12]→10 s、DOUT[19..16]→1 min、DOUT[23..20]→10 min等。

TIMERS的VHDL源程序
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CLKGEN IS
	PORT(CLK: IN STD_LOGIC; --3 MHz信号输入
	     NEWCLK: OUT STD_LOGIC); --100 Hz计时时钟信号输出
END ENTITY CLKGEN;
ARCHITECTURE ART OF CLKGEN IS
	SIGNAL CNT: INTEGER RANGE 0 TO 10#29999#;--十进制计数预制数
	--SIGNAL CNT: INTEGER RANGE 0 TO 10#29#;--十进制计数预制数
	BEGIN
	PROCESS(CLK) IS --分频计数器，由3MHz时钟产生100Hz信号
		BEGIN
		IF CLK'EVENT AND CLK='1' THEN
		 IF CNT=10#29999# THEN CNT<=0; --分频常数为 30000
		 --IF CNT=10#29#THEN CNT<=0;--分频常数为30
		  ELSE CNT<=CNT+1;
		  END IF;
		END IF;
	END PROCESS;
	PROCESS(CNT) IS --计数溢出信号控制
		BEGIN
		IF CNT=10#29999# THEN NEWCLK<='1';
		--IF CNT=10#29# THEN NEWCLK<='1';
		ELSE NEWCLK<='0';
		END IF;
	END PROCESS;
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
	PORT(CLK: IN STD_LOGIC;
		  CLR: IN STD_LOGIC;
		  ENA: IN STD_LOGIC;
		  CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		  CO:OUT STD_LOGIC);
END ENTITY CNT6;
ARCHITECTURE ART OF CNT6 IS
	SIGNAL CQI: STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN
	PROCESS(CLK, CLR, ENA) IS
		BEGIN
		IF CLR='1' THEN CQI<="0000";
		 ELSIF CLK'EVENT AND CLK='1' THEN
		  IF ENA='1' THEN
		     IF CQI="0101" THEN CQI<="0000";
		     ELSE CQI<=CQI+'1'; END IF;
		  END IF;
		END IF;
	END PROCESS;
	PROCESS(CQI) IS
	  BEGIN
	  IF CQI="0000" THEN CO<='1';
	  ELSE CO<='0'; END IF;
	END PROCESS;
	CQ<=CQI;
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
 PORT(CLK:IN STD_LOGIC;
      CLR:IN STD_LOGIC;
      ENA:IN STD_LOGIC;
      CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
      CO:OUT STD_LOGIC);
END ENTITY CNT10;
ARCHITECTURE ART OF CNT10 IS
 SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
 BEGIN
 PROCESS(CLK,CLR,ENA) IS
  BEGIN 
  IF CLR='1' THEN CQI<="0000";
  ELSIF CLK'EVENT AND CLK='1' THEN 
   IF ENA='1' THEN
    IF CQI="1001" THEN
     CQI<="0000";
    ELSE 
     CQI<=CQI+'1';
    END IF;
   END IF;
  END IF;
 END PROCESS;
 PROCESS(CLK,CQI) IS
  BEGIN
  IF CLK'EVENT AND CLK='1' THEN
   IF CQI<"1001" THEN
    CO<='0';
   ELSE
    CO<='1';
   END IF;
  END IF;
 END PROCESS;
 CQ<=CQI;
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTRLS IS
  PORT(CLK: IN STD_LOGIC;      
  SEL: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END ENTITY CTRLS;
ARCHITECTURE ART OF CTRLS IS
  SIGNAL CNT: STD_LOGIC_VECTOR(2 DOWNTO 0);
  BEGIN
  PROCESS(CLK) IS
    BEGIN
    IF CLK'EVENT AND CLK='1' THEN
      IF CNT="111" THEN 
         CNT<="000";
       ELSE 
         CNT<=CNT+'1';
      END IF ;
   END IF;
  END PROCESS;
  SEL<=CNT;
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DISPLAY IS
  PORT(SEL: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
       DATAIN: IN STD_LOGIC_VECTOR(23 DOWNTO 0);
       COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
       SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DISPLAY;
ARCHITECTURE ART OF DISPLAY IS
  SIGNAL DATA:STD_LOGIC_VECTOR(3 DOWNTO 0);
  BEGIN
  PROCESS(SEL) IS
    BEGIN
    CASE SEL IS
      WHEN "000" => COM<="11111110";
      WHEN "001" => COM<="11111101";
      WHEN "010" => COM<="11111011";
      WHEN "011" => COM<="11110111";
      WHEN "100" => COM<="11101111";
      WHEN "101" => COM<="11011111";
      WHEN "110" => COM<="10111111";
      WHEN "111" => COM<="01111111";
      WHEN OTHERS => COM<="11111111";
    END CASE ;
  END PROCESS;
  PROCESS(SEL) IS
    BEGIN
    CASE SEL IS
      WHEN "000" =>DATA<=DATAIN(3 DOWNTO 0);
      WHEN "001" =>DATA<=DATAIN(7 DOWNTO 4);
      WHEN "011" =>DATA<=DATAIN(11 DOWNTO 8);
      WHEN "100" =>DATA<=DATAIN(15 DOWNTO 12);
      WHEN "110" =>DATA<=DATAIN(19 DOWNTO 16);
		WHEN "111" =>DATA<=DATAIN(23 DOWNTO 20);
		
      WHEN OTHERS=>DATA<="1111";
    END CASE;
       CASE DATA IS
      WHEN "0000" => SEG<="00111111";--3FH
      WHEN "0001" => SEG<="00000110";--06H
      WHEN "0010" => SEG<="01011011";--5BH
      WHEN "0011" => SEG<="01001111";--4FH
      WHEN "0100" => SEG<="01100110";--66H
      WHEN "0101" => SEG<="01101101";--6DH
      WHEN "0110" => SEG<="01111101";--7DH
      WHEN "0111" => SEG<="00000111";--07H
      WHEN "1000" => SEG<="01111111";--7FH
      WHEN "1001" => SEG<="01101111";--6FH
      WHEN OTHERS => SEG<="10000000";--00H
   END CASE ;
 END PROCESS;
END ARCHITECTURE ART;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TIMER IS
	PORT(CLR: IN STD_LOGIC;
		  CLK1: IN STD_LOGIC;
		  ENA: IN STD_LOGIC;
		  CLK2:IN STD_LOGIC;
		  COM:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		  SEG:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
		  
END ENTITY TIMER;
ARCHITECTURE ART OF TIMER IS
	COMPONENT CLKGEN IS
		PORT(CLK: IN STD_LOGIC;
			  NEWCLK: OUT STD_LOGIC);
	END COMPONENT CLKGEN;
	COMPONENT CNT10 IS
		PORT(CLK, CLR, ENA: IN STD_LOGIC;
			  CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
			  CO: OUT STD_LOGIC);
	END COMPONENT CNT10;
	COMPONENT CNT6 IS
		PORT(CLK, CLR, ENA: IN STD_LOGIC;
				CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
				CO: OUT STD_LOGIC);
	END COMPONENT CNT6;
	COMPONENT CTRLS IS
		PORT(CLK:IN STD_LOGIC;
			  SEL:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
	END COMPONENT CTRLS;
	COMPONENT DISPLAY IS
		PORT(SEL:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
			  DATAIN:IN STD_LOGIC_VECTOR(23 DOWNTO 0);
			  COM: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
			  SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	END COMPONENT DISPLAY;	
	SIGNAL S0: STD_LOGIC;
	SIGNAL S1, S2, S3, S4, S5: STD_LOGIC;
	SIGNAL S:STD_LOGIC_VECTOR(2 DOWNTO 0);
	SIGNAL DOUT:STD_LOGIC_VECTOR(23 DOWNTO 0);
	BEGIN
	UO: CLKGEN PORT MAP(CLK=>CLK1, NEWCLK=>S0);
	U1: CNT10 PORT MAP(S0,CLR,ENA, DOUT(3 DOWNTO 0), S1);
	U2: CNT10 PORT MAP(S1, CLR, ENA,DOUT(7 DOWNTO 4), S2);
	U3: CNT10 PORT MAP(S2, CLR, ENA, DOUT(11 DOWNTO 8), S3);
	U4: CNT6 PORT MAP(S3, CLR, ENA, DOUT(15 DOWNTO 12), S4);
	U5: CNT10 PORT MAP(S4, CLR,ENA, DOUT(19 DOWNTO 16), S5);
	U6: CNT6 PORT MAP(S5, CLR, ENA, DOUT(23 DOWNTO 20));
	U7: CTRLS PORT MAP(CLK2,S(2 DOWNTO 0));
	U8: DISPLAY PORT MAP(S,DOUT,COM,SEG);
END ARCHITECTURE ART;

仿真结果如图

RTL视图