EE213 Lab3 virtuoso NAND NOR INV XOR HA design&layout（min size layout method）

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已于 2025-05-05 00:50:12 修改

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文章标签： centos 集成测试

于 2025-01-16 22:04:36 首次发布

本文链接：https://blog.youkuaiyun.com/qq_60183616/article/details/145192300

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0 前言

记录一下来到skd上的强度比较大的一门课，数字集成电路2的lab设计还是蛮好的，该帖非详细教程只是单纯的写一些思虑并用作笔记，新手小白欢迎交流，有错勿喷！

1 设计目标

本次主要是设计一个半加器，其中设计半加器是通过很多基础门搭建的，所以展示了各种基础门与非，或非，反相器以及异或门的原理图和版图，并最终通过组合获得最后半加器的版图。同时也分享了通过分析电流的流向共用有源区达到版图最小尺寸的目标。

2 减小面积的layout画法

我们以一个与非门为例，在设计复杂的栅时，建议从弄清楚你想要的电流如何传播开始。红色箭头线显示了电流在这个布局中的移动方式，如图中看到的，2个PMOS并行连接，2个NMOS串联连接。

下图中，在设计布局时，我们可以通过结合2个PMOS的active和pimplant区域，自然地连接两个D;同样的技巧也用于2个NMOS，右侧NMOS的S自然地连接到左侧NMOS的D，因为它们共享active和nimplant，这样的布局可以大大的减小版图的面积

下图显示了一个复杂的gate的另一个例子。箭头线表示当前是如何移动的，你可以仔细分析一下他是怎么做到的，并且尝试自己找个电路图绘制他的最小版图：

3 NAND

3.1 symbol

3.2 schematic

3.3 layout

4 NOR

4.1 symbol

4.2 schematic

4.3 layout

5 INV

5.1 symbol

5.2 schematic

5.3 layout

6 XOR

6.1 symbol

6.2 schematic

6.3 layout

7 HA

7.1 symbol

7.2 schematic

7.3 layout

7.4 hspice simulation

*half adder
.TEMP 25
.OPTIONS ACCURATE
.OPTIONS POST=2

.GLOBAL vdd!

* YOU SHOULD INCLUDE MODLE FILES
*.INCLUDE *'/NMOS_VTL.inc'
*.INCLUDE *'/PMOS_VTL.inc' 

* YOU SHOULD INCLUDE YOUR NELIST
*.INCLUDE halfadder.sp

* YOU SHOULD ADD LOAD CAPACITANCE

* YOU SHOULD GIVE INPUT PATTERNS FOR TEST CASES

* YOU SHOULD GIVE PROPER INPUT PATTERNS FOR MAXIMUM DELAY

.PARAM PERIOD = 20NS
.PARAM T0= 0.1NS
.PARAM T1= T0+PERIOD
.PARAM T2= T1+0.1NS
.PARAM STEP= 1PS
*.PARAM DELAY_MAX =10NS

VDD   VDD! 0 0.7
VGND  GND! 0 0

.TRAN STEP T2

* YOU SHOULD INCLUDE MODEL FILES

.INCLUDE "/home/centos/PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/NMOS_VTL.inc"
.INCLUDE "/home/centos/PDK/FreePDK45/ncsu_basekit/models/hspice/tran_models/models_ff/PMOS_VTL.inc"

* YOU SHOULD INCLUDE YOUR NELIST


** Library name: myLib
** Cell name: INV
** View name: schematic
.subckt INV in out
m0 out in 0 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m1 out in vdd! vdd! PMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends INV
** End of subcircuit definition.

** Library name: myLib
** Cell name: NAND
** View name: schematic
.subckt NAND a b out
m1 net11 b 0 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m0 out a net11 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m3 out b vdd! vdd! PMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m2 out a vdd! vdd! PMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends NAND
** End of subcircuit definition.

** Library name: myLib
** Cell name: NOR
** View name: schematic
.subckt NOR a b out
m1 out b 0 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m0 out a 0 0 NMOS_VTL L=50e-9 W=90e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m3 net12 b vdd! vdd! PMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
m2 out a net12 vdd! PMOS_VTL L=50e-9 W=180e-9 AD=9.45e-15 AS=9.45e-15 PD=300e-9 PS=300e-9 M=1
.ends NOR
** End of subcircuit definition.

** Library name: myLib
** Cell name: XOR
** View name: schematic
.subckt XOR a b out
xi3 net14 net12 INV
xi2 net13 net11 INV
xi1 b net9 INV
xi0 a net10 INV
xi5 net10 net9 net13 NAND
xi4 a b net14 NAND
xi6 net12 net11 out NOR
.ends XOR
** End of subcircuit definition.

** Library name: myLib
** Cell name: HA
** View name: schematic
.subckt HA a b c s
xi0 a b s XOR
xi1 a b net11 NAND
xi2 net11 c INV
.ends HA
** End of subcircuit definition.


xi0 a b cout sum HA
Vin1 A gnd PULSE 0v 0.7v 9.9n 0.1n 0.1n 9.9n 20n
Vin2 B gnd PULSE 0v 0.7v 4.9n 0.1n 0.1n 4.9n 10n
c1 0 cout 10f
c0 sum 0 10f
*.MEASURE POWER_AT_MAX PARAM='TOT_POWER*PERIOD/DELAY_MAX'
* YOU SHOULD MAKE SURE THAT YOU ARE MEASURING THE CORRECT SIGNAL FOR MAXIMUM DELAY. BELOW IS JUST AN EXAMPLE.
.MEASURE TRAN DELAY_COUT TRIG V(B) VAL=0.35v RISE=2 TARG V(cout) VAL=0.35v RISE=1

.END