SRIO—IP核——4.SRIO配置与示例,协议解析

4.SRIO IP核配置

4.1 Basic

4.1.1第一页配置(Basic)

  1. Link Width:链路通道数量
  2. Transfer Frequency:每条通道的波特率
  3. Reference Clock Frequency:外部输入的参考时钟
  4. Buffer Configuration:传输和接收缓存区的深度可以定制为8、16或32.这个数字表示缓冲区能够存储的数据包数量。选择较小的缓冲区深度可以节省资源(主要是块ram和lut),而最大的缓冲区深度可以获得最大的吞吐量
  5. Component Device ID:配置设备ID
  6. Device ID Width:设备ID宽度,应与链接伙伴的设备ID宽度匹配
  7. Unified Clock:如果用户设计为log_clk(主用户时钟)和phy_clk,使用相同的时钟,请勾选此复选框。选择此选项可以显著降低延迟和资源利用率。
  8. Flow Control:这些选项表明了变送器使用的流量控制类型

Transmitter Controlled:选择此选项,core首次尝试使用发射机控制的流控制,如果链接伙伴不支持这种方式,会切换到接收机控制

Receiver Controlled:仅接收控制流量控制时选择此选项。该模式采用盲目传输和重试协议的方式控制报文的流量。

  1. Additional transceiver control and status ports:选中此框可启用额外的收发器控制和状态端口。这些端口对应于相应设备GTX/GTP用户指南中同名的收发器端口。这些端口在调试收发链路时很有用。
4.1.2第二页配置(Shared Logic)

Include Shared Logic in Example Design:MMCM,Reset logic和GT COMMON block作为共享逻辑被包含在example design。

Include Shared Logic in Core:MMCM,Reset logic和GT COMMON block作为共享逻辑被包含在core中。

4.2 Advanced

4.2.1第一页配置(Basic)

Mode:Basic/Advance;选高级,可以对I/O等内容进行配置;但是经验证,Basic模式也挺好,Basic+Share Logic in Core

系统配置:根据实际情况,选择通道数和每个通道的传输速率、以及参考时钟频率。

Buffer配置:选择发送/接收buffer的深度。深度越大,能缓存的数据包就越多;相应的消耗资源也就越多。

设备ID:也就是接口协议里面的源ID,可配为8bit或16bit,但收发双方的设备ID宽度应该相同。

设备ID的位宽:8/16

Unified Clock:选择后,log_clk必须等于phy_clk;选中这个选项可以减少延时和资源利用率。

流控

transmitter-controlled发送器控制的流控:首先使用发送器控制的流控,接收器不支持再切换到接收器控制的流控;

receiver-controlled接收器控制的流控:若选择,则核只支持接收器控制的流控。

transmitter-controlled流控可以利用接收buffer的状态和水印最小化重试条件。receiver-controlled流控会随意的发包并使用重试协议。

4.2.2第二页配置(logic layer)

主要选择源端(source)和目的端(destination)支持的事务类型:

    默认除了最后的(data streaming)都勾选上的。因为data streaming是IP核定义的第九类事务类型而RapidIO协议中的第九类事务为保留。

    下面的支持维护事务要勾选上。

    Enable Arbitration:仲裁使能选项:用来使能逻辑层与输入端口之间的仲裁器。防止多个事务的拥堵,优先级如下所示:

LCSBA:启用后,内核将检查传入的I/O事务的高位地址,如果地址匹配,则将事务路由到维护端口。仅针对HELLO包格式。

4.2.3第三页配置(I/O)

Port I/O style

    Condensed I/O:简要I/O,信号少;

    Initiator/Target:按请求/响应区分通道,各自使用一组AXI4-S接口通道

HELLO Format

Messaging

    Combined with IO:消息事务和I/O写事务采用相同的IO端口

    Separate Messaging Port:消息事务采用一个独立的端口传输。

Maintainance:维护端口类型只能为AXI4-Lite类型。

4.2.4第四页配置(BUF)

Request Reordering

    若选择,发送Buffer会根据请求包的优先级重新排序。这里所说的优先级应该是Xilinx对事务类型自定义的优先级,如下图所示:

Flow Control Options:用于流控的选项

4.2.5第五页配置(PHY)

CRF:关键帧,关键请求流,用于扩展优先级映射,一般不使用。

IDLE:空闲模式,IDLE选择与传输速率有关

IDLE1:只支持每通道线速率小于5.5Gbps的情况,RapidIO使用的控制符号为短控制符号

IDLE2:6.25Gbps的线速率必须选择IDLE2

注意:当IDLE1和IDLE2均被选中时,每通道线速率仅支持小于等于5.5Gbps的情况。

4.2.6第六页配置(log reg)

指定了Device ID与Vendor ID设备标识CAR存储有关RapidIO设备的信息。

    CAR存储有关RapidIO设备子系统创建者/版本的信息等,不影响逻辑功能。

    为了简单,大多默认。

4.2.7第七页配置(PHY reg)

上面主要设置扩展功能地址空间和超时控制等,默认。

Port General Control CSR

    HOST指示该设备是主机设备。如果未设置此位,则设备是代理或从设备。主使能位控制是否允许设备向系统发出请求。如果未设置“主机使能”位,则设备可能仅响应请求。

4.2.8第八页配置(Shared Logic)

一般选择放在Example Design中,一是为了学习理解,二是灵活操作。

主要是将时钟和复位(MMCM,复位逻辑和GTCOMMON模块)之类的共享逻辑放在示例设计中。

5.示例工程Example Design介绍

5.1示例工程架构组成

示例工程目录:

包含两个头文件和一堆子模块。

5.1.1子模块介绍

文件名称

模块功能描述

maintenance_list.vh

Verilog头文件,定义了一些维护事务,它被包含在srio_quick_start.v模块中

instruction_list.vh

Verilog头文件,定义了121个事务,它被包含在srio_request_gen.v模块中

srio_support.v

srio核心模块,包含IP例化以及时钟和复位;

我们使用IP核就是在该模块的基础上进行逻辑设计。

srio_request_gen.v

生成请求事务的模块,把instruction_list.vh中包含的事务发出去

srio_response_gen.v

这个模块用来产生有响应事务的响应包

srio_quick_start.v

这个模块与IP核的维护端口相连,用来发起维护事务

srio_report.v

在仿真时,这个模块用来产生包接受和发送的时间戳,在硬件上运行的时候这个模块可以删除

srio_statistics.v

这个模块用来收集核的统计信息并通过寄存器接口提交一些信息,提交的信息可以通过Vivado的调试特征以及用户设计来访问

srio_sim.v

srio_sim.v是仿真顶层文件,它例化了两个核,分别是primary和mirror,并把它们连接到一起用于仿真。它也包含了上报测试是否成功的机制与超时功能

5.1.2工程结构

整个结构包括时钟模块,复位模块,配置结构以及产生RapidIO事务的激励模块。

    srio_quick_start.v模块在顶层srio_example_top.v中例化,它与IP核的维护端口相连用来产生维护事务,维护事务在maintenance_list.vh中进行定义,用户可以根据需要编辑maintenance_list.vh文件来添加,修改和移除维护事务。

    srio_request_gen.v模块也在顶层srio_example_top.v中例化,它用来产生I/O事务与消息事务。这个模块也存储了期望的响应并把接收的响应与期望值进行比较。

    srio_response_gen.v模块也在顶层srio_example_top.v中例化,它用来为接收到的请求事务生成对应的响应事务。

   

    通过上图可以看出,产生I/O事务有两种方式:(端口类型:AXI4-Stream类型)

    ·通过例子工程中自带的srio_request_gen.v产生I/O事务

    ·通过顶层模块中Initiator和Target的request/response接口自己编写代码产生I/O事务

    同样的,也有两种方式产生维护事务:(端口类型:AXI4-Lite类型t)

    ·通过例子工程中自带的srio_quick_start.v模块产生维护事务

    ·通过顶层模块中的维护接口自己编写代码产生维护事务

默认情况下,示例设计被配置为自动生成刺激(用于I/O和维护事务)并绕过外部接口。通过设置VALIDATION_FEATURES=1和QUICK_STARTUP=1,在srio_example_top.v模块中实现此默认值。此外,有必要注释外部接口以保存引脚并改善定时。

要使用外部接口进行I/O生成,请设置参数VALIDATION_FEATURES=0,并取消注释外部接口(axis_ireq_*,axis_tresp_*,axis_iresp_*,axis_treq_*,axis_iotx_*,和axis_iorx_*)在srio_example_top模块中。要将外部接口用于维护事务,请设置参数QUICK_STARTUP=0,并取消注释外部接口(axis_maintr_*)在srio_example_top模块中。srio_example_top包含有助于此过程的注释。

5.2示例工程仿真分析

5.2.1仿真分析

仿真目录:

仿真顶层例化了两个srio_top实体:一个primary,一个mirror:

    可以看到,primary的发送管脚tx与mirror的接收管脚rx相连接,也就是说由primary发给mirror;另一个方向同样,primary的接收管脚rx与mirror的发送管脚tx相连接。

    按照理解,primary的srio_request_gen.v产生的I/O事务,将由ireq接口发送出去,由mirror的treq接口接收。mirror实体的srio_request_gen.v产生的I/O事务,也由ireq接口发送出去,由primary的treq接口接收。

5.2.2仿真验证

Run Simulation:

添加信号,分组方便查看

然后就等初始化完成,port_initialized拉高,表示初始化完成。Link_initialized拉高,表示物理层接受了7个控制符号并发送了15个控制符号。

    仿真结果,使用第一包数据进行分析

    由图可知,包头信号为64’h006020fcd0000600

    换算成二进制为:64’b0000_0000_0110_0000_0010_0000_1111_1100_1101_16’b0_0110_8’b0

    首先判断事务类型:

    FTYPE=[55:52]=6,  TTYPE=[51:48]=0,

    可以判断,事务类型为SWRITE。(SWRITE没有TTYPE)

我们再把SWRITE事务类型格式拉出来进行对比一下

得知,size=15,意思就是这包请求包含16个字节的数据。而tdata为64bit,8byte;

    可以推论在发送数据的第二个有效时钟周期时,将会拉高tlast。如上图标红②所示。

6.SRIO接口通信协议

6.1 总线技术Rapid IO的含义

逻辑层定义整体协议和数据包格式。这是端点启动和完成事务所必需的信息。

传输层提供数据包从端点移动到端点所需的路由信息。

物理层描述了设备级接口细节,例如数据包传输机制,流控制,电气特性和低级错误管理。

这种划分提供了将新事务类型添加到逻辑规范的灵活性,而无需修改传输或者物理层规范。

6.2 SRIO协议解析

6.2.1 协议原理

1)SRIO协议是基于点对点的串行通信协议,通过高速差分信号进行数据传输

2)SRIO协议采用虚拟通道的方式实现并行传输,每个虚拟通道都有独立的发送和接收缓冲区。

3)SRIO协议支持多种数据传输模式,包括可靠传输和非可靠传输,以满足不同应用场景的需求。

4)SRIO协议通过控制消息和数据消息进行通信,控制消息用于配置和管理通信链路,数据消息用于传输实际数据。

6.2.2 数据传输流程

SRIO协议的数据传输流程包括以下几个步骤:

a)发送端将数据划分为一系列的数据包,并添加头部信息。

b)发送端将数据包发送到接收端,通过SRIO链路进行传输。

c)接收端接收到数据包后,进行数据解析和处理。

d)接收端发送确认消息给发送端,表示数据接收成功。

e)发送端接收到确认消息后,将数据包从发送缓冲区删除。

6.2.3 帧格式

SRIO协议的帧格式包括以下几个字段:

a)控制字段:用于指示帧类型和传输模式。

b)目标ID字段:指示数据包的目标设备ID。

c)源ID字段:指示数据包的源设备ID。

d)虚拟通道ID字段:指示数据包所属的虚拟通道。

e)数据字段:实际的数据内容。

f)校验字段:用于校验数据的完整性。

6.2.4 性能要求

1)SRIO协议在传输速率、延迟和可靠性等方面有着严格的性能要求。

2)传输速率:SRIO协议支持多种传输速率,包括1.25Gbps、2.5Gbps、3.125Gbps等。

3)延迟:SRIO协议要求在数据传输过程中保持低延迟,以确保实时性能。

4)可靠性:SRIO协议通过重传机制和差错校验等方式,确保数据的可靠性。

Core name: Xilinx LogiCORE Serial RapidIO Version: 5.5 Release Date: April 19, 2010 ================================================================================ This document contains the following sections: 1. Introduction 2. New Features 3. Supported Devices 4. Resolved Issues 5. Known Issues 6. Technical Support 7. Other Information (optional) 8. Core Release History 9. Legal Disclaimer ================================================================================ 1. INTRODUCTION For the most recent updates to the IP installation instructions for this core, please go to: http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm For system requirements: http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm This file contains release notes for the Xilinx LogiCORE IP Serial RapidIO v5.5 solution. For the latest core updates, see the product page at: http://www.xilinx.com/rapidio/ 2. NEW FEATURES - ISE 12.1 software support - Designed to RapidIO Interconnect Specification v2.1 - Virtex-6 LXT/HXT/SXT 5.0 Gbps support - Spartan-6 3.125 Gbps and 4x support - Expanded simulator support - Support for ML505, ML605 and SP605 boards (see Release Notes AR for details) 3. SUPPORTED DEVICES - Virtex-6 LXT/HXT/SXT/CXT - Spartan-6 LXT - Virtex-5 LXT/FXT/SXT - Virtex-4 FX 4. RESOLVED ISSUES - PHY does not properly pass CRF bit to Buffer - Version fixed : v5.5 - CR# 519603 - Updated PHY to properly pass CRF - GT settings for Spartan-6 and Virtex-6 updated based on characterization - Version fixed : v5.5 - PORT_INITIALIZED toggles indefinitely - Version fixed : v5.5 - CR# 551271 - GT wrappers updated so that the core will detect invalid data until RESETDONE asserts. - Processing Element Features CAR implemented incorrectly - Version fixed : v5.5 - CR# 528369 - Part of the PEF CAR was implemented in the PHY configuration space, now it is merged into the LOGIO configuration space as directed by the spec. See core User Guide for map of configuration space. - Recommended modifications to Example Design reset scheme - Version fixed : v5.5 - CR# 533208, 533209, 533212 - Updated reset sequence, see AR# 33574 for specifics. - Example design "implement.bat" file has error - Version fixed : v5.5 - CR# 533796 - Corrected syntax for NGDBuild command. - Virtex-6 clock modules not using production MMCM settings - Version fixed : v5.4rev1 - CR#546021 - Using outdated values from the clocking wizard in clock modules. - Buffer BRAM using READ_FIRST mode - Version fixed : v5.4rev1 - CR#546424 - Using READ_FIRST mode for buffer BRAMs - need to update to WRITE_FIRST mode for Spartan-6 and Virtex-6 based on characterization. - VHDL example design simulation error when CRF bit de-selected - Version fixed : v5.4rev1 - CR# 532020 - Updated example design so that CRF signals not added when CRF support is disabled. - Virtex-6 bring-up issues - Version fixed : v5.4 - CR#527725, CR#525309, CR#531695 - Using integer values for the MMCM_ADV, regenerated Virtex-6 wrappers based on general hardware characterization results, revised reset sequence. Please see core Release Notes for updates. - GUI settings incorrect or not properly reflected in hardware. - Version fixed : v5.4 - CR#507334, CR#528369, CR#528370 / AR#32122 - The following register fields were corrected: Re-transmit Suppression mask, Logical Layer extended features pointer, DeviceVendorID. - Latches inferred in VHDL example design - Version fixed: v5.2 - CR#509670 / AR#32189 - Added intermediate values for partial register and combinational assignments. - lnk_trdy_n does not assert in evaluation core simulations - Version fixed : v5.1rev1 - CR#493479 / AR#31864 - Modified initial state in evaluation cores. - PHY won't generate stand-alone due to missing module - Version fixed : v5.1rev1 - CR#493162 / AR#31834 - Shared file between buffer and log added to buffer file list. - Virtex-4 core has long initialization time - Version fixed : v5.1rev1 - CR#481684 / AR#31617 - Virtex-4 initSM modified to prevent branch to silent when RX PCS resets in DISCOVERY state. - LogIO local arbitration doesn't account for valid causing re-arbitration prior to legitimatepacket completion. - Version fixed : v5.1 - CR#478748 - Valid used to gate mresp_eof_n and iresp_eof_n for local arbitration. - A ireq_dsc_n asserted for an undefined packet type does not get propogated by the logical layer. - Version fixed : v5.1 - CR#478541 - undefined packet type decode now passes dsc to buffer allowing packet to be dropped. - 16-bit deviceID cores may see a maintenance response transaction presented but not validated on the IResp interface resulting in a lost transaction. by the logical layer. - Version fixed : v5.1 - CR#474894 - Fixed issue when the maintenance response is followed immediatly by a single DWord SWrite packet. - SourceID not configureable for IReq port. - Version fixed : v5.1 - CR#473938 - Added ireq_src_id port to logical layer. All transmit source IDs should now be configureable and all received destination IDs observable. - Write enables into LogIO registers aren't allowing partial register writes. - Version fixed : v5.1 - CR#473441 - Write enables now implementedfor all LogIO registers allowing byte-wise writes of CSRs such as the deviceID register and BAR. - Message response transaction received as a user defined packet type using 16-bit device IDs appears as a corrupted packet on the IResp interface. - Version fixed : v5.1 - CR#473400, CR#473693 - Fixed LogIO RX to properly handle all user-defined types. - PHY core does not dsc upon retry when coincident with TX packet eof resulting in potential buffer lock-up - Version fixed : v4.4rev2 - CR#478246 / AR#31407 - lnk_tdst_dsc_n now asserted for all retry and error scenarios. - Retry of packet being sent causes packet to get stuck in buffer - Version fixed : v4.4rev2 - CR#477217 / AR#31318 - No longer applicable, v5.1 introduces new buffer. - Core accepts muddled packet when reinitializing during packet receipt - Version fixed : v4.4rev1 - CR#477115 / AR#31308 - Core PNAs packet in receipt when link goes down. - Core LCSBA implementation removes 64MB of possible addressing space. - Version fixed : v4.4 - CR#472992 / AR#30939 - Use 10-bit mask with full 34-bit address for LCSBA intercept. - CRC error on stalled packet - Version fixed : v4.4 - CR#469678 / AR#30940 - Fixed condition which loaded in new CRC sequence on a stall just after sof received by PHY. This is a non-concern for Xilinx buffer users. - Virtex-4 4x core may intermittenly train down to 1x mode - Version fixed : v4.4 - CR#467616 / AR#30314 - Modified oplm_pcs_rst_sequence.v file supplied with the core to register asynchronous TXLOCK and RXLOCK signals. - Re-initialization not forced following a change to Port Width Override - Version fixed : v4.4 - CR#459427 / AR#30323 - Modified PHY Layer to detect a change in the port width override field and reinitialize when updated. - Messaging packets providing incorrect treq_byte_count value - Version fixed : v4.4 - CR#467116 / AR#30320 - Modified Logical Layer to properly decode Messaging size field. Modified testbench to properly check byte count for messaging type packets. - 8-bit SWrite transactions usign 16-bit deviceIDs suffer lost eofs - Version fixed : v4.4 - CR#467668 / AR#30322 - Modified Logical Layer to properly forward eof through the pipeline. - Some Logical Layer CARs are not being set correctly in the core. - Version fixed : v4.4 - CR#458414 / AR#30054 - The following Logical Layer CARs are not being set correctly in the core: - Assembly Information CAR (offset 0xC) - ExtendedFeaturesPtr portion - Processing Element Features CAR (offset 0x10) - Switch Port Information CAR (offset 0x14) - Destination Operations CAR (offset 0x1C) - Switch Route Table Destination ID Limit CAR (offset 0x34) - Core does not have functionality to enable the user to drop unintended packets based on Device ID. - Version fixed: v4.3. - CR#455552 - Added a new port called deviceid which indicates the current Device ID value stored in the Base Device ID CSR. - Receive side buffer design may corrupt packets - user may see corrupted packets from the logical layer when many small packets cause the status FIFO to fill. - Version fixed: v4.2 - CR#447884 / AR#29263 - No longer applicable, v5.1 introduces new buffer. - Repeated, transmitted packet accepted control symbols referencing the same AckID cause loss of AckID sync - The user will see this as potentially duplicated received packets which ultimately result in a port error condition. - Version fixed: v4.2 - CR#444561 / AR#29233 - Modified the transmit encoder to send a single packet accepted symbol per back-to-back control symbol. - Stomped packet sent after RFR (Restart-from-Retry)control symbol - The user will occasionally see error recovery on a retry which will affect system bandwidth. - Version fixed: v4.2 - CR#435188 / AR#24837 - Modified the PHY interface to kill a packet if discontinued on eof and prevent entry to the buffer. 5. KNOWN ISSUES The following are known issues for v5.5 of this core at time of release: - NGDBuild errors when using ISE GUI unless XST Keep Hierarchy set to Soft - Version to be fixed : Fix Not Scheduled - CR#534514 / AR#33528 - Please reference the Answer Record for additional information and recommendations. - Virtex-4 FX 3.125G, 4x core may not meet timing. - Version to be fixed : Fix Not Scheduled - CR#506364 / AR#32195 - Please reference the Answer Record for additional information and recommendations. - Unable to traindown to x1 mode in Lane 2. - Version to be fixed : Fix Not Scheduled - CR#457109 / AR#30023 - Traindown in Lane 0 works successfully but the Serial RapidIO endpoint is unable to traindown to Lane 2. The RocketIO transceivers only allow traindown to the channel bonding master. - Core reinitialization during error recovery causes recoverable protocol error. - Version to be fixed : Fix Not Scheduled - CR#457885 / AR#30021 - This is an corner condition that could occur if core is forced to reinitialize (i.e. - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable. - Post-Synplicity synthesis implementation runs may exhibit ucf failures - Version to be fixed : Fix Not Scheduled - CR#447782 / AR#29522 - Synplicity generated net names are not consistent with XST generated names and may not be consistent between core types. The .ucf file must be edited in these failure cases. Please reference the Serial RapidIO v5.1 web Release Notes for suggested work around. - PNA cause field may occasionally reflect a reserved value - Version to be fixed : Fix Not Scheduled - CR#436767 / AR#24982 - The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols. - Control Symbols may be lost on reinit - Version to be fixed : Fix Not Scheduled - CR#436768 / AR#24970 - This is an unusual and ultimately recoverable error. Set the "Additional Link Request Before Fatal" value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state. - Logical Rx does not support core side stalls - Version to be fixed : Fix Not Scheduled - CR#436770 / AR#24968 - The rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule. The most recent information, including known issues, workarounds, and resolutions for this version is provided in the IP Release Notes Guide located at www.xilinx.com/support/documentation/user_guides/xtp025.pdf 6. TECHNICAL SUPPORT To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines. 7. OTHER INFORMATION - N/A 8. CORE RELEASE HISTORY Date By Version Description ================================================================================ 04/2010 Xilinx, Inc. 5.5 5.0 Gbps support 03/2010 Xilinx, Inc. 5.4 Revision 1 11.5 support/Patch Release 09/2009 Xilinx, Inc. 5.4 Spartan-6 support 06/2009 Xilinx, Inc. 5.3 Virtex-6 support 04/2009 Xilinx, Inc. 5.2 11.1i support 11/2008 Xilinx, Inc. 5.1 Revision 1 Patch Release 09/2008 Xilinx, Inc. 5.1 New Buffer LogiCore 07/2008 Xilinx, Inc. 4.4 Revision 2 Patch Release 07/2008 Xilinx, Inc. 4.4 Revision 1 Patch Release 06/2008 Xilinx, Inc. 4.4 Bug Fixes 03/2008 Xilinx, Inc. 4.3 10.1i support 10/2007 Xilinx, Inc. 4.2 9.2i support 02/2007 Xilinx, Inc. 4.1 9.1i support 02/2006 Xilinx, Inc. 3.1 Revision 1 Patch Release 01/2006 Xilinx, Inc. 3.1 8.1i support ================================================================================ 9. Legal Disclaimer (c) Copyright 2006 - 2010 Xilinx, Inc. All rights reserved. This file contains confidential and proprietary information of Xilinx, Inc. and is protected under U.S. and international copyright and other intellectual property laws. DISCLAIMER This disclaimer is not a license and does not grant any rights to the materials distributed herewith. Except as otherwise provided in a valid license issued to you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under or in connection with these materials, including for any direct, or any indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. CRITICAL APPLICATIONS Xilinx products are not designed or intended to be fail- safe, or for use in any application requiring fail-safe performance, such as life-support or safety devices or systems, Class III medical devices, nuclear facilities, applications related to the deployment of airbags, or any other applications that could lead to death, personal injury, or severe property or environmental damage (individually and collectively, "Critical Applications"). Customer assumes the sole risk and liability of any use of Xilinx products in Critical Applications, subject only to applicable laws and regulations governing limitations on product liability. THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
评论 5
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值