qq_44702247的博客

VHDL学习：14位全加器

VHDL学习记录

刚学习VHDL，第一个实验：两输入与非门LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY yufei ISPORT( a,b:IN STD_LOGIC; y:OUT STD_LOGIC );END;ARCHITECTURE behaver OF yufei ISBEGIN y <= a NAND b;END behaver...

方式一library ieee;use ieee.std_logic_1164.all;entity slect1_4 is port(S1,S2:in std_logic; A,B,C,D:in std_logic; Z:out std_logic);end entity slect1_4;architecture ART of slect1_4 is signal S:std_logic_vector(1 downto 0); begin S <= S1&S2;