IP核之PLL

I P核

IP-PLL

1. 概述

• 锁相环（phase Locked loop）
• 提供了ALTPLL

2. 配置
3. 应用

瞎搞之乱写： 实现控制两个LED闪烁，分别为1S、2S

 
 module Verilog_to_PLL
 (
	CLK_50M,RST_N,LED1,LED2
 );
 
 input CLK_50M;
 input RST_N;
 output LED1;
 output LED2;
 wire CLK_1M;
 
 reg[20:0] time_cnt;
 reg[20:0] time_cnt_n;
 reg led_reg;
 reg led_reg_n;
 reg [2:0] Time_2S;
 reg [2:0] Time_2S_n;
 reg led1_reg;
 reg led1_reg_n;
 parameter SET_TIME_1s=20'd1000_000;
 
 PLL	PLL_inst (
	.inclk0 ( CLK_50M ),
	.c0 (  ),
	.c1 (  ),
	.c2 (CLK_1M)
	);
	
//计数时序	
always@ (posedge CLK_1M or negedge RST_N)
begin
	if(!RST_N)
		time_cnt<=20'h0;
	else
		time_cnt<=time_cnt_n;	
end
//计数组合

always @(*)
begin
	if(time_cnt==SET_TIME_1s)
		time_cnt_n=20'h0;
	else
		time_cnt_n=time_cnt+20'h1;
end



//灯时序
always@ (posedge CLK_1M or negedge RST_N)
begin
	if(!RST_N)
		led_reg<=1'h0;
	else
		led_reg<=led_reg_n;	
end
//灯组合
always@ (*)
begin
	if(time_cnt==SET_TIME_1s)
		led_reg_n=~led_reg;
	else
		led_reg_n=led_reg;
end


//计数时序	
always@ (posedge CLK_1M or negedge RST_N)
begin
	if(!RST_N)
		Time_2S<=2'h0;
	else 
		Time_2S<=Time_2S_n;	
end
//计数组合

always @(*)
begin
	if(Time_2S==2'd2)
		Time_2S_n=2'd0;
	else if(time_cnt==SET_TIME_1s)
		Time_2S_n=Time_2S+2'd1;
	else
		Time_2S_n=Time_2S;
end


//灯时序
always@ (posedge CLK_1M or negedge RST_N)
begin
	if(!RST_N)
		led1_reg<=1'h0;
	else
		led1_reg<=led1_reg_n;	
end
always@ (*)
begin
	if(Time_2S==20'd2)
		led1_reg_n=~led1_reg;
	else
		led1_reg_n=led1_reg;
end




assign LED1=led_reg;
assign LED2=led1_reg;

endmodule