计数器VHDL testbench

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
Port (
led:out std_logic;
switch:in std_logic
);
end test;

architecture Behavioral of test is

begin
process(switch)
begin
if switch=’1’ then
led<=’1’;
else
led<=’0’;
end if;
end process;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test_bench is
end test_bench;

architecture Behavioral of test_bench is
component test port(
led :out std_logic;
switch:in std_logic);
end component;
signal led:std_logic:=’0’;
signal switch:std_logic:=’0’;
begin
dut:test port map(
led=>led,switch=>switch
);
process
begin
switch<=’1’;
wait for 10ms;
switch<=’0’;
wait for 10ms;
end process;
end Behavioral;