qq_42993019的博客

二选一选择器 代码 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity test2 is Port ( a,b,sel:in BIT;y:out bit); end test2; architecture Behavioral of test2 is signal m ,n:bit; begin process(a,b,sel) m<=a an...

library ieee; use ieee.std_logic_1164.all; entity cnt6_tb is end cnt6_tb; architecture rtl of cnt6_tb is component cnt6 port( clr,en,clk :in std_logic; q :out std_logic_vector(2 downto 0) ); end com...

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity test is Port ( led:out std_logic; switch:in std_logic ); end test; architecture Behavioral of test is begin process(switch) begin if switch=’1’ then l...