‘typedef’ was ignored in this declaration

本文深入探讨了C++中结构体定义与typedef的正确用法,解析了一个常见警告错误的原因,并提供了清晰的解决方案。通过理解结构体声明与typedef的关系,读者将学会如何避免在代码中出现类似的警告。
typedef struct Elem{
    Elem(float N,int E)
    :e(E),
    n(N)
    {}
    float e;
    int n;
};

warning:‘typedef’ was ignored in this declaration
原因:结构体没有使用别名
解决:去掉typedef或在括号外加别名

Info: Running Quartus Prime Analysis & Synthesis Info: Version 20.1.0 Build 711 06/05/2020 SJ Lite Edition Info: Processing started: Tue Dec 02 21:48:19 2025 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vending_machine_top -c vending_machine_top Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 16 of the 16 processors detected Warning (10463): Verilog HDL Declaration warning at vending_machine_top.v(11): "enum" is SystemVerilog-2005 keyword Error (10170): Verilog HDL syntax error at vending_machine_top.v(11) near text: "logic"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at vending_machine_top.v(17) near text: "}"; expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at vending_machine_top.v(29) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10149): Verilog HDL Declaration error at vending_machine_top.v(46): identifier "HAVE_5" is already declared in the present scope Error (10149): Verilog HDL Declaration error at vending_machine_top.v(51): identifier "HAVE_10" is already declared in the present scope Error (10149): Verilog HDL Declaration error at vending_machine_top.v(56): identifier "HAVE_15" is already declared in the present scope Error (10149): Verilog HDL Declaration error at vending_machine_top.v(61): identifier "HAVE_20" is already declared in the present scope Error (10170): Verilog HDL syntax error at vending_machine_top.v(117) near text: "@"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at vending_machine_top.v(148) near text: "begin"; expecting ".", or "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10170): Verilog HDL syntax error at vending_machine_top.v(150) near text: "="; expecting ".", or an identifier. Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (10112): Ignored design unit "vending_machine_top" at vending_machine_top.v(1) due to previous errors Info (12021): Found 0 design units, including 0 entities, in source file vending_machine_top.v Error: Quartus Prime Analysis & Synthesis was unsuccessful. 11 errors, 2 warnings Error: Peak virtual memory: 4714 megabytes Error: Processing ended: Tue Dec 02 21:48:25 2025 Error: Elapsed time: 00:00:06 Error: Total CPU time (on all processors): 00:00:13 Error (293001): Quartus Prime Full Compilation was unsuccessful. 13 errors, 2 warnings
最新发布
12-03
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