FPGA学习之路(四)之点灯大法

写在前面

QAQ，折腾FPGA好几天，才想起来，有个Flag还没做——点灯，于是就折腾了下。原理啥的就不说了，直接贴代码和结果。

Verilog

`timescale 1ns / 1ps
module light_led(
	RST_N, //复位信号，低电平
	CLK, //时钟信号
	LED //LED信号
);

input RST_N;
input CLK;
output LED;

reg [31:0] Counter;
reg LED;

//脉冲计数器
always @(posedge CLK or negedge RST_N)
	begin
		if(!RST_N)
			begin
				Counter <= 0;
			end
		else if(Counter == 32'd99_999_999)
			begin
				Counter <= 0;
			end
		else
			begin
				Counter <= Counter + 1;
			end
	end
//LED灯控制(0:亮 1:灭)
always @(posedge CLK or negedge RST_N)
	begin
		if(!RST_N)
			begin
				LED <= 1;
			end
		else if(Counter == 32'd49_999_999)//第一秒
			begin
				LED <= 0;
			end
		else if(Counter == 32'd99_999_999)
			begin
				LED <= 1;
			end
	end
endmodule

TESTBENCH

// Copyright (C) 2017  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details.

// *****************************************************************************
// This file contains a Verilog test bench template that is freely editable to  
// suit user's needs .Comments are provided in each section to help the user    
// fill out necessary details.                                                  
// *****************************************************************************
// Generated on "08/10/2020 14:03:45"
                                                                                
// Verilog Test Bench template for design : light_led
// 
// Simulation tool : ModelSim-Altera (Verilog)
// 

`timescale 1 ps/ 1 ps
module light_led_tb();
// constants                                           
// general purpose registers
// test vector input registers
reg CLK;
reg RST_N;
// wires                                               
wire LED;

// assign statements (if any)                          
light_led i1 (
// port map - connection between master ports and signals/registers   
	.CLK(CLK),
	.LED(LED),
	.RST_N(RST_N)
);
initial                                                
begin                                                  
	RST_N <= 0;
	#10;
	RST_N <= 1;
	CLK <= 0;
$display("Running testbench");                       
end  
                                                  
always #20 CLK <= !CLK;//20ps=50M  
                                                                                                                 
endmodule

RTL视图

RTL仿真结果