FPGA实验之串口接收

FPGA实验之串口接收

串口数据的接收采样在每个数据位的中间，这样能够采集到比较准确的数据。

（1）    建立工程

（2）    编写程序

module UART_receive(input CLK,RST,RXD,

                                            output Receive_done,Odd_data,

                                            output [7:0]Receive_data);

//parameter BPS9600=13'd5208; //每位数据传输时间为t=1/9600 s,周期T=1/50000000，计数值为t/T=5208

parameter BPS115200=9'd434;//每位数据传输时间为t=1/115200 s,周期T=1/50000000，计数值为t/T=434

reg [31:0]C1;

reg [7:0]ii;

reg H2L1,H2L2;

reg receive_done,odd_data;

reg [7:0]receive_data;

 

always @(posedge CLK or negedge RST)

       if(!RST)

              begin C1<=32'd0;ii<=0; receive_done<=0; receive_data<=8'b0; odd_data<=1'b0;end 

       else

              case(ii)

              0: if(!RXD) beginii<=ii+1;end

              1: if(C1==BPS115200)begin C1<=32'd0; ii<=ii+1; end //起始位，，没做处理，直接忽略

                     elseC1<=C1+1;

              2,3,4,5,6,7,8,9:begin

                     if(C1==BPS115200-1)begin C1<=32'd0; ii<=ii+1; end //接收数据位

     &