FPGA AD0809 Verilog implement

//该列子在quatus ii 11上编译通过哦

module AD0809(

clk, //脉宽（至少100ns）
rst_n,
EOC, //约100us后EOC变为高电平转换结束
START, //启动信号，上升沿有效（至少100ns）
OE, //高电平打开三态缓冲器输出转换数据
ALE, //高电平有效，选择信道口
ADDA, //因为ADDA,ADDC都选择接地了，这里只有ADDA为变量
DATA, //转换数据
DATA_R
);


output START,OE,ALE,ADDA;
input EOC,clk,rst_n;
input [7:0] DATA;
output [7:0] DATA_R;


reg START,OE,ALE,ADDA;
reg[7:0] DATA_R;




reg [4:0] CS,NS;


parameter IDLE = 5'b00001,START_H = 5'b00010,START_L = 5'b00100,CHECK_END = 5'b01000,GET_DATA = 5'b10000;


always @(*)
case(CS)
IDLE: NS = START_H;
START_H: NS = CHECK_END;
CHECK_END:
if(EOC)
NS = GET_DATA;
else
NS = CHECK_END;


GET_DATA:
NS = IDLE;
default:
NS = IDLE;
endcase


always @(posedge clk)
if(!rst_n)
CS <= IDLE;
else
CS <= NS;




always @(posedge clk)
case(NS)
IDLE:
begin
OE <= 0;
START <= 0;
ALE <= 0;ADDA <= 1;
end


START_H:
begin
OE <= 0;
START <= 1; //产生启动信号
ALE <= 1;ADDA <= 1;//选择信道口IN0
end


START_L:
begin
OE <= 0;
START <= 0;
ALE <= 1; //启动信号脉宽要足够长，在启动的时候ALE要一直有效
end


CHECK_END:
begin
OE <= 0;
START <= 0;
ALE <= 0;
end


GET_DATA:
begin
OE <= 1; //高电平打开三太缓冲器输出转换
DATA_R <= DATA;//提取转换数据
START <= 0;
ALE <= 0;
end


default:
begin
OE <= 0;
START <= 0;
ALE <= 0;ADDA <= 0;
end

endcase

endmodule