OS学习笔记：Lecture 7

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最新推荐文章于 2024-06-21 14:46:44 发布

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本文详细介绍了操作系统中中断和异常处理的基本概念和技术实现，包括硬件中断、软件中断、异常处理流程、中断优先级分配等内容，并探讨了不同类型的中断屏蔽机制。

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IPC

Twomodels:

Shared memory: 不会过多干预

Message passing: 有message这个抽象，有mailbox，需要通过receive和send两个接口操作

Send 通过os的buffer

Receiver blocking non-blocking

Exception

CPU在执行每段指令时都可能调入interrupt handler

Exception table: 包含exception和interrupt

Exception number: 32-127, 129-255 hardware; 128(0x80) systemcall

IDT(interrupt descriptor table) 日常可见的都存储虚拟地址，除了cr3

Exception handler

The processorpushes a return address on the stack (%eip)

not allow to let an application know itself is interrupted

Users are not trustful

Exception handlers run in kernel mode

Kernel stack: trap frame

Source of events cause user->kernel

Device interrupt (pysical pins in CPU)
1. Nonmaskable interrupt (NMI) input pin
2. Interrupt (INTR) input pin
Software interrupt: exception
Program faults

Xv6: initialize the exception table

Interrupt

We must program the device to generate an interrupt, providean interrupt number for it.

Early boards

PIC

8259A chip controls every device's interrupt

PIC can be cascaded (connected by pins)

Master: 0-7

Slave: 8-15

APIC, IO-APIC, LAPIC

8259A cannot meet the need of multi-kernel

Advanced PIC

Local APIC, IO-APIC

Interrupt routing

Priority

Assigning IRQs to devices

Hardware-dependent

Some IRQs are fixed by the architecture

IRQ0: timer

IRQ2: cascade pin for 8259A

Interrupt priority

Software interrupt	high
NMI
INTR
TRAP flag	Low

EOI: end of interrupt: CPU->PIC

If IRQ come from master: only send to master

If IRQ come from slave: send to slave and master

Nested interrupt

a second interrupt occurs when an interrupt routine isexcuting

Maximizing parallelism

Re-entry: 导致代码复杂性高任何callback机制都可能会产生

同时处理同样问题导致上锁

Interrupts can be interrupted

By different interrupts

Exceptions can be interrupted

Exceptions can nest two levels deep

Triple fault

Things never to do in an OS

Panic

Interrupt masking

Two different types

Global

Selective

Three crucial data-structures

Global descriptor table (GDT)

Interrupt descriptor table (IDT)

Task-state segment (TSS)