HDLBits-Verilog:Count15

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于 2024-12-12 11:43:19 发布

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分类专栏： hdlbits-verilog 文章标签： fpga开发 hdlbits 刷题 verilog 学习

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Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is synchronous, and should reset the counter to 0.

module top_module (
    input clk,
    input reset,      // Synchronous active-high reset
    output [3:0] q);

    always@(posedge clk)begin
        if(reset)begin
            q<=4'd0;
        end
        else begin
            q<=q+1'b1;
        end
    end
endmodule