#include"userpar.h"
#include"userflash.h"
#include"bitband.h"
#include"math.h"
#include"usersys.h"
#include"string.h"
#include"useruart_inter.h"
#define CTL_TEMP_UP_LIMIT 15//µ¥Î»1¡æ
#define CTL_TEMP_DOWN_LIMIT 13//µ¥Î»1¡æ
#define WARN_TEMP_UP_LIMIT 70//µ¥Î»1¡æ
#define VOL_UP_LIMIT 20.0f//
#define VOL_DOWN_LIMIT 16.0 //
#define CURR_UP_LIMIT 60.0f//µ¥Î»0.1A
typedef struct
{
uint16_t FPGA_AD[20] ;
float rd_power ; //·´Ïò¹¦ÂÊAD
float fd_power ; //ÕýÏòÏò¹¦ÂÊAD
float vol_a;
float curr ;
float fan_curr1 ;
float fan_curr2 ;
int8_t temp ;
uint8_t pa_att_set,pa_att_ack;
uint8_t pa_ctl_soft_set,pa_ctl_soft_ack;//ÓÐÈí¼þ¿ØÖƹ¦·Å¿ªÆô¹Ø±Õʱ,±ØÐëpanel_bon´ò¿ª²ÅÐÐ
uint8_t vol_warn ;//1 ¸æ¾¯ 0Õý³£
uint8_t curr_warn ;//1 ¸æ¾¯ 0Õý³£
uint8_t temp_warn ;//1 ¸æ¾¯ 0Õý³£
// uint8_t in_power_warn ;//1 ¸æ¾¯ 0Õý³£
uint8_t swr_state,swr_warn;//1 ¸æ¾¯ 0Õý³£
uint8_t pwm_state,pwm_warn;//1 ¸æ¾¯ 0Õý³£
uint8_t fan_ctl_set;//ͨ¹ýζÈÅжÏÊÇ·ñ¿ªÆô·ç»ú,Óɵ¥Æ¬»úÖ÷¶¯
uint8_t fan_ctl_ack;//FPGAÓ¦´ð
uint8_t pa_warn_mcu;//(¹¦·Å1µçÔ´µçѹ ¹¦·Å1µçÔ´µçÁ÷ ¹¦·Å1ζÈ)Òì³£ÐèÒªÖ÷¶¯¹Ø±Õ¹¦·Å ÓÉMCUÖ÷¶¯
uint8_t pa_warn_fpga;//FPGAÓ¦´ð
uint8_t panel_bon ;//0Çå³ý±¨¾¯×´Ì¬ 1 ±£³Ö±¨¾¯×´Ì¬
//uint8_t pa_sw;
uint8_t pa_warn;
//uint8_t fd_power_bfb;
//uint8_t alc_wt_set,alc_wt_ack;
//float in_power;
//float knob_detec;
uint32_t CH1Freq;
uint8_t workmode;
uint8_t is_valid_vol_data;
uint8_t data_Refresh;
}ModuParType;
ModuParType ModuPar;
typedef struct
{
uint32_t flag_s;
uint32_t pa_sw_timer_1s;
uint32_t flag_e;
}Powerdown_saveparType;
Powerdown_saveparType Powerdown_savepar;
#define min_power_input_dbm_ch1 -40
#define max_power_input_dbm_ch1 10
#define min_power_output_dbm_ch1 30
#define max_power_output_dbm_ch1 49
#define step_power_input_ch1 1
#define step_power_output_ch1 1
#define input_dbm_ch1_db_len (((max_power_input_dbm_ch1-min_power_input_dbm_ch1)/step_power_input_ch1 ) + 1)
#define output_dbm_ch1_db_len (((max_power_output_dbm_ch1-min_power_output_dbm_ch1)/step_power_output_ch1) + 1)
typedef struct
{
uint32_t flag_s;
float ch1_jb_fd_power[100];
float ch1_jb_dlt[100];
uint32_t flag_e;
}swrpar_Type;
swrpar_Type swrpar;
typedef struct
{
uint32_t flag_s;
float ch1_input__power_vol[50][100];
float ch1_output_power_vol[50][100];
uint32_t flag_e;
}powercalpar_Type;
powercalpar_Type powercalpar;
float tmp_power_vol_ch1_input[100];
float tmp_power_vol_ch1_output[] =
{
497 ,
513 ,
524 ,
535 ,
546 ,
568 ,
590 ,
612 ,
639 ,
672 ,
704 ,
737 ,
781 ,
830 ,
879 ,
945 ,
1016,
1097,
1179,
1343
};
#define det_len 10
typedef struct
{
float fd_power[det_len];
float rd_power[det_len];
// float in_power[det_len];
float avg_fd,avg_rd;
float sum_fd,sum_rd;
uint32_t cnt;
}powerdetType;
powerdetType powerdet;
#define vol_curr_avg_len 40
typedef struct
{
float vol_a_code[vol_curr_avg_len];
//float vol_b_code[vol_curr_avg_len];
float curr_code[vol_curr_avg_len];
float fun_curr_code[vol_curr_avg_len];
float avg_vol_a,avg_curr,avg_fun_curr;
float sum_vol_a,sum_curr,sum_fun_curr;
uint32_t cnt;
}volcurr_detType;
volcurr_detType volcurr_det;
//void userpar_SetPASw(uint8_t tmp)
//{
// if(ModuPar.pa_warn > 0)
// {
// ModuPar.pa_sw = 0;
// }
// else
// {
// ModuPar.pa_sw = tmp;
// }
//}
//uint8_t userpar_GetPASw(void)
//{
// return ModuPar.pa_sw;
//}
void userpar_SetPACtl_Soft(uint8_t tmp)
{
ModuPar.pa_ctl_soft_set = tmp;
ModuPar.pa_warn_mcu = 0;
ModuPar.vol_warn = 0;
ModuPar.curr_warn = 0;
ModuPar.temp_warn = 0;
ModuPar.pa_warn = 0;
ModuPar.swr_warn = 0;
ModuPar.pwm_warn = 0;
ModuPar.pa_ctl_soft_ack = ModuPar.pa_ctl_soft_set + 1;
useruart_inter_Set(cmd02,ModuPar.pa_ctl_soft_set);
}
void userpar_SetPAAtt_Soft(uint8_t tmp)
{
if(tmp > MAX_ATT)
{
tmp = MAX_ATT;
}
ModuPar.pa_att_set = tmp;
}
uint8_t userpar_GetPAAtt_Soft(void)
{
return ModuPar.pa_att_set;
}
void userpar_AckPAAtt_Soft(uint8_t tmp)
{
ModuPar.pa_att_ack = tmp;
}
uint8_t userpar_Get_AckPAAtt_Soft(void)
{
return ModuPar.pa_att_ack;
}
uint8_t userpar_GetPACtl_Soft(void)
{
return ModuPar.pa_ctl_soft_set;
}
void userpar_AckPACtl_Soft(uint8_t tmp)
{
ModuPar.pa_ctl_soft_ack = tmp;
}
uint8_t userpar_Get_AckPACtl_Soft(void)
{
return ModuPar.pa_ctl_soft_ack;
}
void userpar_SetPanle_Bon(uint8_t Bon)
{
if(Bon == 1)
{
ModuPar.pa_warn_mcu = 0;
ModuPar.vol_warn = 0;
ModuPar.curr_warn = 0;
ModuPar.temp_warn = 0;
ModuPar.swr_warn = 0;
ModuPar.pwm_warn = 0;
ModuPar.pa_ctl_soft_set = 0;
ModuPar.pa_ctl_soft_ack = 0;
ModuPar.pa_warn = 0;
}
// else
// {
// if((ModuPar.panel_bon == 0) && (Bon == 1))
// {
// ModuPar.pa_ctl_soft_set = 1;
// }
// }
ModuPar.panel_bon = Bon;
}
uint8_t userpar_GetPanle_Bon(void)
{
return ModuPar.panel_bon;
}
uint16_t userpar_GetFD_Power(void)
{
return ModuPar.fd_power*10;
}
uint16_t userpar_GetRD_Power(void)
{
return ModuPar.rd_power*10;
}
uint16_t userpar_GetPA_Vol(void)
{
// if(ModuPar.vol_a > ModuPar.vol_b)
// {
// return ModuPar.vol_a*10;
// }
// else
// {
// return ModuPar.vol_b*10;
// }
return ModuPar.vol_a*10.0f;
}
uint16_t userpar_GetPA_Curr(void)
{
return ModuPar.curr*10;
}
uint8_t userpar_GetPA_State(void)
{
return (ModuPar.swr_state << 4) | (ModuPar.pwm_state << 3) | (ModuPar.vol_warn << 2) | (ModuPar.curr_warn << 1) | (ModuPar.temp_warn << 0);
}
int8_t userpar_GetTemp(void)
{
return ModuPar.temp;
}
uint8_t userpar_GetFun1_Curr(void)
{
return ModuPar.fan_curr1*10;
}
uint8_t userpar_GetFun2_Curr(void)
{
return ModuPar.fan_curr1*10;
}
uint8_t userpar_Get_Ack_PAState(void)
{
return ModuPar.pa_warn_fpga;
}
uint8_t userpar_Get_Set_PAState(void)
{
return ModuPar.pa_warn_mcu;
}
uint8_t userpar_Get_Ack_FunCtl(void)
{
return ModuPar.fan_ctl_ack;
}
uint8_t userpar_Get_Set_FunCtl(void)
{
return ModuPar.fan_ctl_set;
}
void userpar_Ack_PACtl(uint8_t tmp)
{
ModuPar.pa_warn_fpga = tmp;
}
void userpar_Ack_FunCtl(uint8_t tmp)
{
ModuPar.fan_ctl_ack = tmp;
}
void userpar_Init(void)
{
userpar_loadCfg();
userpar_SetFreq(100);
ModuPar.fan_ctl_set = 1;
ModuPar.pa_warn_mcu = 0;
ModuPar.fan_ctl_ack = ModuPar.fan_ctl_set + 1;
ModuPar.pa_warn_fpga = ModuPar.pa_warn_mcu + 1;
ModuPar.panel_bon = 1;
ModuPar.swr_warn = 0;
ModuPar.pwm_warn = 0;
ModuPar.vol_warn = 0;
ModuPar.curr_warn = 0;
ModuPar.temp_warn = 0;
ModuPar.pa_warn = 0;
ModuPar.pa_ctl_soft_set = 0;
ModuPar.pa_ctl_soft_ack = ModuPar.pa_ctl_soft_set + 1;
///ModuPar.in_power_warn = 0;
//ModuPar.alc_wt_set = 0;
// ModuPar.alc_wt_ack = ModuPar.alc_wt_set + 1;
ModuPar.data_Refresh = FALSE;
userpar_Set_workmode(normal_work_mode);
userpar_loadCfg_powerdownpar();
userpar_Erase_powerdownpar();
UserTimer_SetPeroid(TIMER_PA_OPEN_PERIOD,TIMER_PA_OPEN_OPT);
UserTimer_SetPeroid(TIMER_ABNORMAL_PERIOD,TIMER_ABNORMAL_OPT);
ModuPar.is_valid_vol_data = FALSE;
}
void userpar_SetFPGA_AD(uint8_t ad_index,uint16_t AD_Value)
{
ModuPar.FPGA_AD[ad_index] = AD_Value;
if(ad_index == 12)
{
ModuPar.data_Refresh = TRUE;
}
}
void userpar_Set_FPGA_ACK_state(uint8_t swr_state,uint8_t pwm_state)
{
//ModuPar.swr_state = 0;
//ModuPar.pwm_state = 0;
}
void userpar_SetTemp(int8_t temp)
{
//ModuPar.temp = temp;
}
//uint8_t *userpar_advol_input_ch1(void)
//{
// return (uint8_t*)&powerdet.avg_in;
//}
uint8_t *userpar_advol_output_ch1(void)
{
return (uint8_t*)&powerdet.avg_fd;
}
void userpar_AbNormal_Handle(void)
{
double vol = ModuPar.vol_a;
if(UserTimer_InqIsTrigger(TIMER_ABNORMAL_OPT) == TRUE)
{
ModuPar.is_valid_vol_data = TRUE;
}
if(ModuPar.is_valid_vol_data == FALSE)
{
return;
}
// if(ModuPar.pa_sw == 0)
// {
// return;
// }
if(ModuPar.temp > CTL_TEMP_UP_LIMIT)
{
ModuPar.fan_ctl_set = 1;
}
else if(ModuPar.temp < CTL_TEMP_DOWN_LIMIT)
{
ModuPar.fan_ctl_set = 0;
}
if(vol >= VOL_UP_LIMIT)
{
ModuPar.vol_warn = 1;
ModuPar.pa_warn_mcu = 1;
}
else if(vol <= VOL_DOWN_LIMIT)
{
ModuPar.vol_warn = 1;
ModuPar.pa_warn_mcu = 1;
}
if(ModuPar.temp >= WARN_TEMP_UP_LIMIT)
{
ModuPar.temp_warn = 1;
ModuPar.pa_warn_mcu = 1;
}
if(ModuPar.pwm_state > 0)
{
ModuPar.pwm_warn = 1;
ModuPar.pa_warn_mcu = 1;
}
// if(ModuPar.in_power >= IN_POWER_MAX)
// {
// ModuPar.in_power_warn = 1;
// ModuPar.pa_warn_mcu = 1;
// }
if(ModuPar.swr_state > 0)
{
ModuPar.swr_warn = 1;
ModuPar.pa_warn_mcu = 1;
}
if(ModuPar.pa_warn_mcu > 0)
{
ModuPar.pa_ctl_soft_set = 0;
ModuPar.pa_ctl_soft_ack = 0;
}
ModuPar.pa_warn = (ModuPar.vol_warn<<4) | (ModuPar.curr_warn<<3) | (ModuPar.temp_warn << 2) | (ModuPar.pwm_warn << 1) | (ModuPar.swr_warn << 0);
}
uint8_t userpar_getPaState(void)
{
return ModuPar.pa_warn;
}
void userpar_ParCal_Handle(void)
{
float vol;
//float dlt_bfb;
uint16_t curr_code;
uint32_t i =0;
if(ModuPar.data_Refresh == FALSE)
{
return;
}
ModuPar.data_Refresh = FALSE;
ModuPar.temp = (ModuPar.FPGA_AD[11]*2.5f*1.0f/4095.0f - 0.5f)/0.01f;
if(powerdet.cnt >= det_len)
{
for(i = 0;i < (det_len - 1);i++)
{
powerdet.fd_power[i] = powerdet.fd_power[i+1];
powerdet.rd_power[i] = powerdet.rd_power[i+1];
}
powerdet.fd_power[(det_len - 1)] = ModuPar.FPGA_AD[9];
powerdet.rd_power[(det_len - 1)] = ModuPar.FPGA_AD[8];
}
else
{
powerdet.fd_power[powerdet.cnt] = ModuPar.FPGA_AD[9];
powerdet.rd_power[powerdet.cnt] = ModuPar.FPGA_AD[8];
powerdet.cnt++;
}
powerdet.sum_fd = 0;
powerdet.sum_rd = 0;
for(i = 0;i < powerdet.cnt;i++)
{
powerdet.sum_fd = powerdet.sum_fd + powerdet.fd_power[i];
powerdet.sum_rd = powerdet.sum_rd + powerdet.rd_power[i];
}
powerdet.avg_fd = powerdet.sum_fd*2.5f/4095.0f/powerdet.cnt;
powerdet.avg_rd = powerdet.sum_rd*2.5f/4095.0f/powerdet.cnt;
ModuPar.fd_power = userpar_compute_outputpower_ch1(powerdet.avg_fd);
ModuPar.rd_power = userpar_compute_outputpower_ch1(powerdet.avg_rd);
uint8_t *pcal_fd;
uint8_t *pcal_dlt_thr;
pcal_fd = userpar_correct_ch1_jb_fd_power();
pcal_dlt_thr = userpar_correct_ch1_jb_dlt();
if((ModuPar.fd_power > (*pcal_fd)) && (ModuPar.fd_power < (ModuPar.rd_power + (*pcal_dlt_thr))))
{
ModuPar.swr_state = 1;
}
ModuPar.swr_state = 0;
curr_code = ModuPar.FPGA_AD[0] + ModuPar.FPGA_AD[1] + ModuPar.FPGA_AD[2] + ModuPar.FPGA_AD[3] +
ModuPar.FPGA_AD[4] + ModuPar.FPGA_AD[5] + ModuPar.FPGA_AD[6] + ModuPar.FPGA_AD[7];
if(volcurr_det.cnt >= vol_curr_avg_len)
{
for(i = 0;i < (vol_curr_avg_len - 1);i++)
{
volcurr_det.vol_a_code[i] = volcurr_det.vol_a_code[i+1];
//volcurr_det.vol_b_code[i] = volcurr_det.vol_b_code[i+1];
volcurr_det.curr_code[i] = volcurr_det.curr_code[i+1];
volcurr_det.fun_curr_code[i] = volcurr_det.fun_curr_code[i+1];
}
volcurr_det.vol_a_code[(vol_curr_avg_len - 1)] = ModuPar.FPGA_AD[10];
//volcurr_det.vol_b_code[(vol_curr_avg_len - 1)] = ModuPar.FPGA_AD[6];
volcurr_det.curr_code[(vol_curr_avg_len - 1)] = curr_code;//ModuPar.FPGA_AD[0];
volcurr_det.fun_curr_code[(vol_curr_avg_len - 1)] = ModuPar.FPGA_AD[12];
}
else
{
volcurr_det.vol_a_code[volcurr_det.cnt] = ModuPar.FPGA_AD[10];
//volcurr_det.vol_b_code[volcurr_det.cnt] = ModuPar.FPGA_AD[6];
volcurr_det.curr_code[volcurr_det.cnt] = curr_code;//ModuPar.FPGA_AD[0];
volcurr_det.fun_curr_code[volcurr_det.cnt] = ModuPar.FPGA_AD[12];
volcurr_det.cnt++;
}
volcurr_det.sum_vol_a = 0;
//volcurr_det.sum_vol_b = 0;
volcurr_det.sum_curr = 0;
volcurr_det.sum_fun_curr = 0;
for(i = 0;i < volcurr_det.cnt;i++)
{
volcurr_det.sum_vol_a = volcurr_det.sum_vol_a + volcurr_det.vol_a_code[i];
//volcurr_det.sum_vol_b = volcurr_det.sum_vol_b + volcurr_det.vol_b_code[i];
volcurr_det.sum_curr = volcurr_det.sum_curr + volcurr_det.curr_code[i];
volcurr_det.sum_fun_curr = volcurr_det.sum_fun_curr + volcurr_det.fun_curr_code[i];
}
volcurr_det.avg_vol_a = volcurr_det.sum_vol_a/volcurr_det.cnt;
//volcurr_det.avg_vol_b = volcurr_det.sum_vol_b/volcurr_det.cnt;
volcurr_det.avg_curr = volcurr_det.sum_curr/volcurr_det.cnt;
volcurr_det.avg_fun_curr = volcurr_det.sum_fun_curr/volcurr_det.cnt;
vol = (volcurr_det.avg_curr*2.5f/4095.f);
vol = vol*6.0f;//2.0f·Öѹ±¶Êý
if(vol >= 19.968f)//19.52f->8¸öͨµÀ0µçÁ÷µçѹ(AD²É¼¯µçѹ*2(·Öѹ±¶Êý)*8(8ͨµÀ))
{
ModuPar.curr = (vol - 19.968f)*1.166f/0.1f;
}
else
{
ModuPar.curr = 0;
}
ModuPar.fan_curr1 = volcurr_det.avg_fun_curr*2.5f/4095;
if(ModuPar.fan_curr1 > 1.229f)
{
ModuPar.fan_curr1 = (ModuPar.fan_curr1 - 1.229f)*2/0.18f;
}
else
{
ModuPar.fan_curr1 = 0;
}
ModuPar.curr = ModuPar.curr + ModuPar.fan_curr1;
ModuPar.vol_a = (volcurr_det.avg_vol_a*2.5f/4095.0f) * 31.0f;
}
void userpar_pa_open_handle(void)
{
if(UserTimer_InqIsTrigger(TIMER_PA_OPEN_OPT) == TRUE)
{
UserTimer_SetPeroid(TIMER_PA_OPEN_PERIOD,TIMER_PA_OPEN_OPT);
if(ModuPar.pa_ctl_soft_set == 1)
{
Powerdown_savepar.pa_sw_timer_1s++;
}
}
}
uint32_t userpar_get_pa_run_timer_1s(void)//0.1Сʱ
{
return Powerdown_savepar.pa_sw_timer_1s/360;//0.1Сʱ
}
void userpar_handle(void)
{
userpar_pa_open_handle();
userpar_ParCal_Handle();
// userpar_compute_inputpower_ch1_base_vol();
userpar_compute_outputpower_ch1_base_vol();
userpar_AbNormal_Handle();
}
void userpar_SavePower_vol(void)
{
userflash_Erase(CORRECT_DATA_SAVESECTOR_CAL_5);
userflash_Write(0,(uint8_t*)&powercalpar,sizeof(powercalpar_Type),CORRECT_DATA_SAVEADDR_CAL_5);
}
#define MIN_FREQ 18000
#define MAX_FREQ 40000
void userpar_SetFreq(uint32_t freq)
{
if((freq < MIN_FREQ) || (freq > MAX_FREQ))
{
return;
}
ModuPar.CH1Freq = freq;
}
uint32_t userpar_GetFreq(void)
{
return ModuPar.CH1Freq;
}
uint32_t userpar_freqindex_correct(void)
{
uint32_t freq_index;
freq_index = 0;
return freq_index;
}
uint8_t *userpar_correct_detectvol_inputpower_ch1(int8_t power_dbm)
{
uint16_t freq_index,power_index;
freq_index = userpar_freqindex_correct();
power_index = (power_dbm-min_power_input_dbm_ch1)/step_power_input_ch1;
return (uint8_t*)&powercalpar.ch1_input__power_vol[freq_index][power_index];
}
uint8_t *userpar_correct_detectvol_outputpower_ch1(int8_t power_dbm)
{
uint16_t freq_index,power_index;
freq_index = userpar_freqindex_correct();
power_index = (power_dbm-min_power_output_dbm_ch1)/step_power_output_ch1;
return (uint8_t*)&powercalpar.ch1_output_power_vol[freq_index][power_index];
}
void userpar_compute_inputpower_ch1_base_vol(void)
{
uint16_t index,i;
float vol_cal;
double Divide_0_freq;
double step_freq = 1;
index = userpar_freqindex_correct();
for(i = 0;i < input_dbm_ch1_db_len;i++)
{
if(index == 0)
{
Divide_0_freq = 100.0f;
step_freq = 50.0f;
}
else if(index == 1)
{
Divide_0_freq = 150.0f;
step_freq = 50.0f;
}
else if(index == 2)
{
Divide_0_freq = 200.0f;
step_freq = 300.0f;
}
else if(index == 3)
{
Divide_0_freq = 500.0f;
step_freq = 500.0f;
}
else if(index == 4)
{
Divide_0_freq = 1000.0f;
step_freq = 4000.0f;
}
else if(index == 5)
{
Divide_0_freq = 5000.0f;
step_freq = 5000.0f;
}
else if(index == 6)
{
Divide_0_freq = 10000.0f;
step_freq = 10000.0f;
}
else if(index == 7)
{
Divide_0_freq = 20000.0f;
step_freq = 30000.0f;
}
else if(index == 8)
{
Divide_0_freq = 50000.0f;
step_freq = 50000.0f;
}
else if(index == 9)
{
Divide_0_freq = 100000.0f;
step_freq = 100000.0f;
}
else if(index == 10)
{
Divide_0_freq = 200000.0f;
step_freq = 100000.0f;
}
else if(index == 11)
{
Divide_0_freq = 300000.0f;
step_freq = 100000.0f;
}
else if(index == 12)
{
Divide_0_freq = 400000.0f;
step_freq = 0;
}
if(index == 12)
{
vol_cal = powercalpar.ch1_input__power_vol[index][i];
}
else
{
vol_cal = powercalpar.ch1_input__power_vol[index][i] +
(powercalpar.ch1_input__power_vol[index + 1][i] - powercalpar.ch1_input__power_vol[index][i])*(ModuPar.CH1Freq-Divide_0_freq)/step_freq;
}
tmp_power_vol_ch1_input[i] = vol_cal;
}
}
void userpar_compute_outputpower_ch1_base_vol(void)
{
uint16_t index,i;
float vol_cal;
double Divide_0_freq;
double step_freq = 1;
// index = userpar_freqindex_correct();
// tmp_power_vol_ch1_output[i] = vol_cal;
}
float userpar_compute_inputpower_ch1(float detect_vol)
{
uint16_t i;
float power_dbm,dlt_db;
if(detect_vol >= tmp_power_vol_ch1_input[input_dbm_ch1_db_len-1])
{
power_dbm = max_power_input_dbm_ch1;
}
else if(detect_vol <= tmp_power_vol_ch1_input[0])
{
power_dbm = min_power_input_dbm_ch1;
}
else
{
for(i = 0;i < (input_dbm_ch1_db_len - 1);i++)
{
if((detect_vol <= tmp_power_vol_ch1_input[i+1]) && (detect_vol >= tmp_power_vol_ch1_input[i]))
{
dlt_db = (detect_vol - tmp_power_vol_ch1_input[i])/(tmp_power_vol_ch1_input[i+1] - tmp_power_vol_ch1_input[i]);
power_dbm = min_power_input_dbm_ch1 + i + dlt_db;
break;
}
}
}
return power_dbm;
}
float userpar_compute_outputpower_ch1(float detect_vol)
{
uint16_t i;
float power_dbm,dlt_db;
if(detect_vol >= tmp_power_vol_ch1_output[output_dbm_ch1_db_len-1])
{
power_dbm = max_power_output_dbm_ch1;
}
else if(detect_vol <= tmp_power_vol_ch1_output[0])
{
power_dbm = min_power_output_dbm_ch1;
}
else
{
for(i = 0;i < (output_dbm_ch1_db_len - 1);i++)
{
if((detect_vol <= tmp_power_vol_ch1_output[i+1]) && (detect_vol >= tmp_power_vol_ch1_output[i]))
{
dlt_db = (detect_vol - tmp_power_vol_ch1_output[i])/(tmp_power_vol_ch1_output[i+1] - tmp_power_vol_ch1_output[i]);
power_dbm = min_power_output_dbm_ch1 + i + dlt_db;
break;
}
}
}
//power_dbm = 12.0f;
return power_dbm;
}
void userpar_loadCfg(void)
{
uint8_t i,j;
userflash_Read(0,(uint8_t*)&powercalpar,sizeof(powercalpar_Type),CORRECT_DATA_SAVEADDR_CAL_5);
if((powercalpar.flag_s != 123456789) || (powercalpar.flag_e != 123456789))
{
powercalpar.flag_s = 123456789;
powercalpar.flag_e = 123456789;
for( j = 0;j < 50;j++)
{
for( i = 0;i < 100;i++)
{
powercalpar.ch1_input__power_vol[j][i] = 2.5f;
powercalpar.ch1_output_power_vol[j][i] = 2.5f;
}
}
}
userflash_Read(0,(uint8_t*)&swrpar,sizeof(swrpar_Type),CORRECT_DATA_SAVEADDR_CAL_6);
if((swrpar.flag_s != 123456789) || (swrpar.flag_e != 123456789))
{
swrpar.flag_s = 123456789;
swrpar.flag_e = 123456789;
for(j = 0;j < 50;j++)
{
swrpar.ch1_jb_dlt[j] = 2;
swrpar.ch1_jb_fd_power[j] = 43;
}
}
}
uint8_t *userpar_correct_ch1_jb_fd_power(void)
{
uint16_t freq_index;
freq_index = 0;
return (uint8_t*)&swrpar.ch1_jb_fd_power[freq_index];
}
uint8_t *userpar_correct_ch1_jb_dlt(void)
{
uint16_t freq_index;
freq_index = 0;
return (uint8_t*)&swrpar.ch1_jb_dlt[freq_index];
}
void userpar_Save_swrPar(void)
{
userflash_Erase(CORRECT_DATA_SAVESECTOR_CAL_6);
userflash_Write(0,(uint8_t*)&swrpar,sizeof(swrpar_Type),CORRECT_DATA_SAVEADDR_CAL_6);
}
void userpar_Erase_mcu_update_pack(void)
{
userflash_Erase(MCU_UPDATE_PACK_SAVESECTOR);
}
void userpar_write_mcu_update_pack(uint32_t pack_bytes,uint8_t *buf,uint32_t offset_addr)
{
userflash_Write(offset_addr,(uint8_t*)buf,pack_bytes,MCU_UPDATE_PACK_SAVEADDR);
}
void userpar_write_mcu_update_bytes(uint32_t total_pack_bytes,uint32_t offset_addr)
{
userflash_Write(offset_addr,(uint8_t*)&total_pack_bytes,4,MCU_UPDATE_PACK_SAVEADDR);
}
void userpar_write_mcu_update_flag_write(uint32_t offset_addr,uint32_t mcu_update_flag)
{
userflash_Write(offset_addr,(uint8_t*)&mcu_update_flag,4,MCU_UPDATE_PACK_SAVEADDR);
}
uint8_t userpar_Get_workmode(void)
{
return ModuPar.workmode;
}
uint8_t userpar_Set_workmode(uint32_t tmp)
{
if(tmp == normal_work_mode)
{
ModuPar.workmode = tmp;
return TRUE;
}
else if(tmp == uddate_work_mode)
{
ModuPar.workmode = tmp;
return TRUE;
}
return FALSE;
}
void userpar_loadCfg_powerdownpar(void)
{
uint16_t i,j;
userflash_Read(0,(uint8_t*)&Powerdown_savepar,sizeof(Powerdown_saveparType),CORRECT_DATA_SAVEADDR_CAL_4);
if((Powerdown_savepar.flag_s != 123456789) || (Powerdown_savepar.flag_e != 123456789))
{
Powerdown_savepar.flag_s = 123456789;
Powerdown_savepar.flag_e = 123456789;
Powerdown_savepar.pa_sw_timer_1s = 0;
}
}
void userpar_Erase_powerdownpar(void)
{
userflash_Erase(CORRECT_DATA_SAVESECTOR_CAL_4);
}
void userpar_SaveCfg_powerdownpar(void)
{
//userflash_Erase(CORRECT_DATA_SAVESECTOR_CAL_4);
userflash_Write(0,(uint8_t*)&Powerdown_savepar,sizeof(Powerdown_saveparType),CORRECT_DATA_SAVEADDR_CAL_4);
}
void HAL_PWR_PVDCallback(void)
{
userpar_SaveCfg_powerdownpar();
}
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