32位ALU设计

设计思路及代码

module ALU32(
ALUcont,A,B,
zero,result
	);
    input [31:0] A,B;
    input [2:0] ALUcont;
    output reg[31:0] result;
    output reg zero;
    
always@(*)
begin
    case(ALUcont)
        //AND
        3'b000:
            begin
            result=A&B;
            zero=(result==0)?1:0;
            end
        //OR
        3'b001:
            begin
            result=A|B;
            zero=(result==0)?1:0;
            end
        //+
        3'b010:
            begin
            result=A+B;
            zero=(result==0)?1:0;
            end
        //not used
        //3'b011:
        //AND !
        3'b100:
            begin
         	result=A&(~B);
            zero=(result==0)?1:0;
            end
        //OR !
        3'b101:
            begin
            result=A|(~B);
            zero=(result==0)?1:0;
            end
        //-
        3'b110:
            begin
            result=A-B;
            zero=(A==B)?1:0;
            end
        //SLT
        3'b111:
            begin
                if(A[31]==1&&B[31]==0)
                    result=1;
                else if(A[31]==0&&B[31]==0)
                    result=0;
                else 
                    result=(A<B)?1:0;
                zero=(result==0)?1:0;
            end
    endcase
end
endmodule        
    

测试代码及表格补全

Test	ALUcont	A	B	result	zero
ADD 0+0	2	00000000	00000000	00000000	1
ADD 0+(-1)	2	00000000	FFFFFFFF	FFFFFFFF	0
ADD 1+(-1)	2	00000001	FFFFFFFF	00000000	1
ADD FF+1	2	000000FF	00000001	00000100	0
SUB 0-0	6	00000000	00000000	00000000	1
SUB 0-(-1)	6	00000000	FFFFFFFF	00000001	0
SUB 1-1	6	00000001	00000001	00000000	1
SUB 100-1	6	00000100	00000001	000000ff	0
SLT 0,0	7	00000000	00000000	00000000	1
SLT 0,1	7	00000000	00000001	00000001	0
SLT 0,-1	7	00000000	FFFFFFFF	00000000	1
SLT 1,0	7	00000001	00000000	00000000	1
SLT -1,0	7	FFFFFFFF	00000000	00000001	0
AND FFFFFFFF,FFFFFFFF	0	FFFFFFFF	FFFFFFFF	FFFFFFFF	0
AND FFFFFFFF,12345678	0	FFFFFFFF	12345678	12345678	0
AND 12345678,87654321	0	12345678	87654321	02244220	0
AND 00000000,FFFFFFFF	0	00000000	FFFFFFFF	00000000	1
OR FFFFFFFF,FFFFFFFF	1	FFFFFFFF	FFFFFFFF	FFFFFFFF	0
OR 12345678,87654321	1	12345678	87654321	97755779	0
OR 00000000,FFFFFFFF	1	00000000	FFFFFFFF	FFFFFFFF	0
OR 00000000,00000000	1	00000000	00000000	00000000	1

module ALU32_test(
    );
    reg [2:0] ALUcont;
    reg [31:0] A,B;
    wire [31:0] result;
    wire zero;
    ALU32 alu(ALUcont,A,B,zero,result); 
    initial
    begin
    //add
        ALUcont=3'b010;
        A=32'h00000000;
        B=32'h00000000;
    #20 A=32'h00000000;
        B=32'hffffffff;
    #20 A=32'h00000001;
        B=32'hffffffff;
    #20 A=32'h000000ff;
        B=32'h00000001;
    //sub
    #20 ALUcont=3'b110;
        A=32'h00000000;
        B=32'h00000000;
    #20 A=32'h00000000;
        B=32'hffffffff;
    #20 A=32'h00000001;
        B=32'h00000001;
    #20 A=32'h00000100;
        B=32'h00000001;
    //slt
    #20 ALUcont=3'b111;
        A=32'h00000000;
        B=32'h00000000;
    #20 A=32'h00000000;
        B=32'h00000001;
    #20 A=32'h00000000;
        B=32'hffffffff;
    #20 A=32'h00000001;
        B=32'h00000000;
    #20 A=32'hffffffff;
        B=32'h00000000;
    //and
    #20 ALUcont=3'b000;
        A=32'hffffffff;
        B=32'hffffffff;
    #20 A=32'hffffffff;
        B=32'h12345678;
    #20 A=32'h12345678;
        B=32'h87654321;
    #20 A=32'h00000000;
        B=32'hffffffff;
    //or
    #20 ALUcont=3'b001;
        A=32'hffffffff;
        B=32'hffffffff;
    #20 A=32'h12345678;
        B=32'h87654321;
    #20 A=32'h00000000;
        B=32'hffffffff;
    #20 A=32'h00000000;
        B=32'h00000000;
    end
endmodule
    

仿真波形图

678;
B=32’h87654321;
#20 A=32’h00000000;
B=32’hffffffff;
#20 A=32’h00000000;
B=32’h00000000;
end
endmodule

仿真波形图