HDLBits刷题笔记8:Circuits.Sequential Logic.Latches and Flip-Flops

D flip-flop

module top_module (
    input clk,
    input d,
    output reg q );
    always @(posedge clk)
        q <= d;
endmodule

D flip-flops

建立一个8bit的D触发器

module top_module (
    input clk,
    input [7:0] d,
    output reg [7:0] q
);
    always @(posedge clk)
        q <= d;
endmodule

DFF with reset

建立一个8bit的D触发器，带同步高电平复位

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output reg [7:0] q
);
    always @(posedge clk)
        if(reset)
            q <= 0;
    	else
            q <= d;
endmodule

DFF with reset value

建立一个下降沿触发的8bit的D触发器，带同步高电平复位，复位时，将触发器的值设置为0x34

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output reg [7:0] q
);
    always @(negedge clk)
        if(reset)
            q <= 8'h34;
    	else
            q <= d;
endmodule

DFF with asynchronous reset

建立一个8bit的D触发器，带异步高电平复位

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output reg [7