makefile

all:clean elab run verdi

elab:

        vcs -full64 -sverilog -l comp.log -f ./filename.f -timescale=1ns/1ps -debug_acc+all -deraceclockdata -top TB_NAME

run:

        ./simv -l run.log

verdi:

        verdi -sverilog -f ./filename.f -ssf wave.fsdb &

clean:

        rm -rf simv*

        rm -rf *.vpd

        rm -rf *.key

        rm -rf csrc

nv_sim:

        ncverilog -sv +define+NC_VERILOG +access+wrc +nctimescale+1ns/1ps -f filename.f

nv_clean:

        rm -rf ./INCA_libs ./*.shm

执行：

1.make nv_sim

2.simvision + load wave.shm

注：在tb中需要加上如下代码

`ifndef NC_VERILOG

initial begin

        $fsdbDumpfile("wave.fsdb");

        $fsdbDumpMDA();

        $fsdbDumpvars;

end

`else

initial begin

        $shm_open("wave.shm");

        $shm_probe(example_tb, "AS");

end

`endif