ARM hint instruction-WFI(Wait For Interrupt)指令详解

本文详细解析ARM架构中的WFI指令,探讨其作为Hint指令的作用,如何让CPU进入standby模式等待中断,并介绍唤醒事件、使用注意事项及唤醒机制。

WFI(Wait For Interrupt)指令是ARM中的一个Hint 指令,内核执行hint指令的时候不需要依赖额外的处理操作。WFI指令可以让CPU进入standby 模式,即低功耗模式,此时内核会暂停其他活动,一直等待中断事件的发生,检测到中断发生后,WFI指令执行完成,CPU退出standby模式。

本文将从ARM hint指令、WFI的用途以及WFI的唤醒事件等三个角度解释WFI指令。

目录

一,ARM Hint 指令

二,WFI指令的用途

standby 模式- 待机模式

三,WFI指令的唤醒事件

四,WFI使用注意事项


一,ARM Hint 指令

HINT 指令可以合法地被视为 NOP指令,但它们可以具有特定于实现的效果,常见的HINT指令有:

  •  NOP // No operation,无操作, 不保证CPU会花时间去执行
  • YIELD // 提示当前线程正在执行可以换出的任务
  • WFE // Wait for Event,进入low power状态,直到等待的事件发生
  • WFI // Wait for interrupt,进入low power状态,直到等待的中断或与中断类似的操作发生
  • SEV // Send Event,发送事件,与WFE对应
  • SEVL // Send Event Local,发送本地事件,与WFE对应

ARM 汇编语言中包含可用于让core进入低功耗状态(low-power state)的指令:WFI或WFE。ARM架构将这些指令定义为hint指令,这意味着core在执行它们时不需要采取任何特定操作。然而,在 Cortex-A 处理器系列中,这些指令的实现方式是关闭几乎所有内核部分的时钟。这意味着内核的功耗显着降低,仅消耗静态漏电流,没有动态功耗。
 

二,WFI指令的用途

WFI指令的主要目的就是使core进入standby模式,直到中断或者类似中断的事件发送,才退出,core继续工作。

standby 模式- 待机模式

在待机模式下,core保持上电状态,但其大部分时钟停止或者进入时钟门限。这意味着core的绝大部分都处于static state,唯一消耗的功率是用于寻找中断唤醒条件的泄漏电流和少量逻辑时钟。

使用 WFI(等待中断)或 WFE(等待事件)指令可以进入此模式。 ARM 建议在 WFI 或 WFE 之前使用数据同步屏障 (Data Synchronization Barrier ,DSB) 指令,以确保待处理的内存事务在更改状态之前完成。

core进入待机状态后,会停止执行,直到检测到唤醒事件。唤醒条件取决于进入指令。对于 WFI,需要中断事件或外部调试请求来唤醒core。对于 WFE,存在许多指定的事件,包括cluster中执行 SEV 指令的另一个core。

WFI 指令广泛用于电池供电的系统。例如,手机可以每秒多次将core置于待机模式,同时等待用户按下按钮才唤醒core,从而可以节省功耗。

WFE 类似于 WFI。core暂停执行,直到发生事件。这可以是列出的事件条件之一,也可以是cluster中另一个core发出的事件信号。其他core可以通过执行 SEV 指令来发出事件信号。 SEV 向所有core发送一个事件信号。还可以对generic timer通用定时器进行编程,以触发将core从 WFE 唤醒的周期性事件。

总而言之,WFI 指令可以提示hint core在接收到中断或类似的exception之前无需执行任何操作,具体来说有两部分:

  1. 强制暂停core的运行以及所有相关的总线活动。
  2. 暂停处理器执行指令。

三,WFI指令的唤醒事件

WFI可以使core进入待机状态,而将core从待机状态中唤醒,则需要中断事件或者类似中断事件的exception(debug事件):

  1. 物理的IRQ中断,但是忽略 CPSR寄存器的 I 位.
  2. 物理的FIQ中断,但是忽略 CPSR寄存器的 F 位.
  3. 物理的异步abort,但是忽略 CPSR寄存器的 A 位.
  4. 异步的调试事件(debug event),当启用侵入式调试(invasive debug)并允许调试事件时,比如Trace 32中的 break 操作,也会将core唤醒。
  5. 包括其他实现定义的硬件机制来生成 WFI 唤醒事件.

四,WFI使用注意事项

  1. 在WFI指令之前使用 DSB 、DMB等内存屏障指令,使得core在进入待机模式之前,完成内存交互。
  2. 当硬件检测到WFI唤醒事件后,WFI指令才算执行完成。
  3. WFI唤醒事件不能被CPSR中的相关掩码(I F A)等bit 位屏蔽,即忽略CPSR中的IFA相关bit 位。
  4. ARM架构并未定义低功耗状态的确切性质,但 WFI 指令的执行不得导致内存一致性遭受破坏。
  5. 如果是为了测试中断事件而使用WFI,注意在中断发生和WFI之间不应有耗时事件(如大量的printf打印),否则有可能导致中断丢失,即中断已经处理完成了才执行WFI指令,此时中断已经消失了,但是WFI还在一直等中断。use case如下:
    1. 当检测到中断时,WFI指令才算完成,才会唤醒处理器,假设有这样一个use case:
      Timer(10); // 假设这是个timer,10秒后将发起中断,中断handler在其他地方定义
      WFI();   //如果处理器没有接收到中断,WFI指令将没有完成,一直处于休眠状态,下一条printf也不会被执行
      printf("中断发生,WFI检测到中断"); 
      正常情况下是可以看到打印的,但是,在timer和WFI之间加入一个耗时事件:
      Timer(10); // 10秒后将发起中断
      WasteTime(20); // 执行这个函数需要20秒
      WFI();   //从中断发生,到处理完成中断用不了10秒,执行到WFI时,中断已经消失了,所以CPU会一直处于休眠状态,下面的printf也不会被执行
      printf("中断发生,WFI检测到中断"); 

/**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File * @version V4.10 * @date 18. March 2015 * * @note * ******************************************************************************/ /* Copyright (c) 2009 - 2014 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: - Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. - Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. - Neither the name of ARM nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ---------------------------------------------------------------------------*/ #ifndef __CORE_CMINSTR_H #define __CORE_CMINSTR_H /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @{ */ #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ /* ARM armcc specific functions */ #if (__ARMCC_VERSION < 400677) #error "Please use ARM Compiler Toolchain V4.0.677 or later!" #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ #define __NOP __nop /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ #define __WFI __wfi /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ #define __WFE __wfe /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ #define __SEV __sev /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ #define __ISB() do {\ __schedule_barrier();\ __isb(0xF);\ __schedule_barrier();\ } while (0) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ #define __DSB() do {\ __schedule_barrier();\ __dsb(0xF);\ __schedule_barrier();\ } while (0) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ #define __DMB() do {\ __schedule_barrier();\ __dmb(0xF);\ __schedule_barrier();\ } while (0) /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ #define __REV __rev /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) { rev16 r0, r0 bx lr } #endif /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) { revsh r0, r0 bx lr } #endif /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] value Value to rotate \param [in] value Number of Bits to rotate \return Rotated value */ #define __ROR __ror /** \brief Breakpoint This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __breakpoint(value) /** \brief Reverse bit order of value This function reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) #define __RBIT __rbit #else __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end result = value; // r will be reversed bits of v; first get LSB of v for (value >>= 1; value; value >>= 1) { result <<= 1; result |= value & 1; s--; } result <<= s; // shift when v's highest bits are zero return(result); } #endif /** \brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __clz #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief LDR Exclusive (8 bit) This function executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) /** \brief LDR Exclusive (16 bit) This function executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) /** \brief LDR Exclusive (32 bit) This function executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) /** \brief STR Exclusive (8 bit) This function executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXB(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (16 bit) This function executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXH(value, ptr) __strex(value, ptr) /** \brief STR Exclusive (32 bit) This function executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ #define __STREXW(value, ptr) __strex(value, ptr) /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ #define __CLREX __clrex /** \brief Signed Saturate This function saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT __ssat /** \brief Unsigned Saturate This function saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT __usat /** \brief Rotate Right with Extend (32 bit) This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ #ifndef __NO_EMBEDDED_ASM __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) { rrx r0, r0 bx lr } #endif /** \brief LDRT Unprivileged (8 bit) This function executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ #define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) /** \brief LDRT Unprivileged (16 bit) This function executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ #define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) /** \brief LDRT Unprivileged (32 bit) This function executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ #define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) /** \brief STRT Unprivileged (8 bit) This function executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRBT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (16 bit) This function executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRHT(value, ptr) __strt(value, ptr) /** \brief STRT Unprivileged (32 bit) This function executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ #define __STRT(value, ptr) __strt(value, ptr) #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ /* GNU gcc specific functions */ /* Define macros for porting to both thumb1 and thumb2. * For thumb1, use low register (r0-r7), specified by constrant "l" * Otherwise, use general registers, specified by constrant "r" */ #if defined (__thumb__) && !defined (__thumb2__) #define __CMSIS_GCC_OUT_REG(r) "=l" (r) #define __CMSIS_GCC_USE_REG(r) "l" (r) #else #define __CMSIS_GCC_OUT_REG(r) "=r" (r) #define __CMSIS_GCC_USE_REG(r) "r" (r) #endif /** \brief No Operation No Operation does nothing. This instruction can be used for code alignment purposes. */ __attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); } /** \brief Wait For Interrupt Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ __attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { __ASM volatile ("wfi"); } /** \brief Wait For Event Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ __attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { __ASM volatile ("wfe"); } /** \brief Send Event Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ __attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { __ASM volatile ("sev"); } /** \brief Instruction Synchronization Barrier Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ __attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { __ASM volatile ("isb 0xF":::"memory"); } /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); } /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ __attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { __ASM volatile ("dmb 0xF":::"memory"); } /** \brief Reverse byte order (32 bit) This function reverses the byte order in integer value. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); #else uint32_t result; __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); #endif } /** \brief Reverse byte order (16 bit) This function reverses the byte order in two unsigned short values. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief Reverse byte order in signed short value This function reverses the byte order in a signed short value with sign extension to integer. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (short)__builtin_bswap16(value); #else uint32_t result; __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); #endif } /** \brief Rotate Right in unsigned value (32 bit) This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. \param [in] value Value to rotate \param [in] value Number of Bits to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { return (op1 >> op2) | (op1 << (32 - op2)); } /** \brief Breakpoint This function causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached. \param [in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. */ #define __BKPT(value) __ASM volatile ("bkpt "#value) /** \brief Reverse bit order of value This function reverses the bit order of the given value. \param [in] value Value to reverse \return Reversed value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end result = value; // r will be reversed bits of v; first get LSB of v for (value >>= 1; value; value >>= 1) { result <<= 1; result |= value & 1; s--; } result <<= s; // shift when v's highest bits are zero #endif return(result); } /** \brief Count leading zeros This function counts the number of leading zeros of a data value. \param [in] value Value to count the leading zeros \return number of leading zeros in value */ #define __CLZ __builtin_clz #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief LDR Exclusive (8 bit) This function executes a exclusive LDR instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (16 bit) This function executes a exclusive LDR instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDR Exclusive (32 bit) This function executes a exclusive LDR instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STR Exclusive (8 bit) This function executes a exclusive STR instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (16 bit) This function executes a exclusive STR instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); return(result); } /** \brief STR Exclusive (32 bit) This function executes a exclusive STR instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location \return 0 Function succeeded \return 1 Function failed */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); return(result); } /** \brief Remove the exclusive lock This function removes the exclusive lock which is created by LDREX. */ __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } /** \brief Signed Saturate This function saturates a signed value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (1..32) \return Saturated value */ #define __SSAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Unsigned Saturate This function saturates an unsigned value. \param [in] value Value to be saturated \param [in] sat Bit position to saturate to (0..31) \return Saturated value */ #define __USAT(ARG1,ARG2) \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ __RES; \ }) /** \brief Rotate Right with Extend (32 bit) This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { uint32_t result; __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return(result); } /** \brief LDRT Unprivileged (8 bit) This function executes a Unprivileged LDRT instruction for 8 bit value. \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint8_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (16 bit) This function executes a Unprivileged LDRT instruction for 16 bit values. \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t result; #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); #else /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not accepted by assembler. So has to use following less efficient pattern. */ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); #endif return ((uint16_t) result); /* Add explicit type cast here */ } /** \brief LDRT Unprivileged (32 bit) This function executes a Unprivileged LDRT instruction for 32 bit values. \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); return(result); } /** \brief STRT Unprivileged (8 bit) This function executes a Unprivileged STRT instruction for 8 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (16 bit) This function executes a Unprivileged STRT instruction for 16 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); } /** \brief STRT Unprivileged (32 bit) This function executes a Unprivileged STRT instruction for 32 bit values. \param [in] value Value to store \param [in] ptr Pointer to location */ __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); } #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ /* IAR iccarm specific functions */ #include <cmsis_iar.h> #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ /* TI CCS specific functions */ #include <cmsis_ccs.h> #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ /* TASKING carm specific functions */ /* * The CMSIS functions have been implemented as intrinsics in the compiler. * Please use "carm -?i" to get an up to date list of all intrinsics, * Including the CMSIS ones. */ #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ /* Cosmic specific functions */ #include <cmsis_csm.h> #endif /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ #endif /* __CORE_CMINSTR_H */ 这段代码什么意思 可以修改吗
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