HDLBITS conwaylife

module top_module(
    input clk,
    input load,
    input [255:0] data,
    output [255:0] q ); 
    
    wire [255:0] q_n[9:1];
    
    assign q_n[8] = {q[15:0], q[255:16]};
    assign q_n[2] = {q[239:0], q[255:240]};
    assign q_n[5] = q;
    always@(*)  begin
        for(int i = 15; i>=0; i = i-1) begin
            q_n[4][i*16+15-:16] = {q_n[5][i*16], q_n[5][i*16+15-:15]};
            q_n[6][i*16+15-:16] = {q_n[5][i*16+14-:15], q_n[5][i*16+15]};
            q_n[7][i*16+15-:16] = {q_n[8][i*16], q_n[8][i*16+15-:15]};
            q_n[9][i*16+15-:16] = {q_n[8][i*16+14-:15], q_n[8][i*16+15]};
            q_n[1][i*16+15-:16] = {q_n[2][i*16], q_n[2][i*16+15-:15]};
            q_n[3][i*16+15-:16] = {q_n[2][i*16+14-:15], q_n[2][i*16+15]};
        end
    end
    
    always@(posedge clk) begin
        if(load == 1) q <= data;
        else begin
            for(int i = 255; i>=0; i--) begin
            	case(q_n[1][i] + q_n[2][i] + q_n[3][i] +q_n[4][i] + q_n[6][i] + q_n[7][i] + q_n[8][i] + q_n[9][i])
                	2:q[i] <= q[i];
                	3:q[i] <= 1'b1;
                	default q[i] <= 1'b0;
            	endcase
        	end
        end
    end

endmodule