Memory Model

1 Preliminary

• Computer Architecture A Quantitative Approach, 5th Edition()

2 Memory Model

2.1 Three Aspects

Atomicity

Visibility

Ordering

2.2 General Model(Weaker)

1. The hardware threads can each perform reads and writes out-of-order, oreven speculatively (before preceding conditional branches have been resolved). In contrast to TSO, where there is no local reordering except of reads after writes to different addresses, here any local reordering is allowed unless specified otherwise.
2. The memory system (perhaps involving a hierarchy of buffers and a complex interconnect) does not guarantee that a write becomes visible to all other hardware threads at the same time point; these architectures are not multiple-copy atomic.
   

3 Two aspects

3.1 CPU Memory Model

3.1.1 Implementation