UVM学习整理——附录（部分组件源码）

最新推荐文章于 2024-10-14 16:14:13 发布

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最新推荐文章于 2024-10-14 16:14:13 发布

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分类专栏：芯片验证-UVM 文章标签：集成测试模块测试功能测试

本文链接：https://blog.youkuaiyun.com/lizhao_yang_/article/details/121567810

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本文详细介绍了UVM中的部分组件源码，包括Driver和Sequencer的握手机制，TLM通信方式，以及uvm_monitor, uvm_sequencer, uvm_scoreboard, uvm_agent, uvm_env和uvm_test的基本功能和特点。重点讨论了Driver和Sequencer之间的交互，如端口类型、数据传输和一对一连接关系，并提供了相关方法的使用说明。" 116274392,8633062,理解Linux的open权限,"['Linux系统', '文件系统', '编程', '权限管理']

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部分组件源码

这些组件源码，除了uvm_driver、uvm_agent、uvm_subscriber中增补定义了部分变量，以提高代码的可重用性之外，其余组件源码的内容基本一致，不存在太大变化。

1.Driver和Sequencer

Driver和Sequencer之间的握手机制：Driver的seq_item_port和Sequencer的seq_item_export：

uvm_driver的源代码：

// Definition of uvm_driver
class uvm_driver #(type REQ=uvm_sequence_item,
                   type RSP=REQ) extends uvm_component;
  // Port: seq_item_port
  // Derived driver classes should use this port to request items from the
  // sequencer. They may also use it to send responses back.
 
  uvm_seq_item_pull_port #(REQ, RSP) seq_item_port;
 
  // Port: rsp_port
  // This port provides an alternate way of sending responses back to the
  // originating sequencer. Which port to use depends on which export the
  // sequencer provides for connection.
 
  uvm_analysis_port #(RSP) rsp_port;
  REQ req;
  RSP rsp;
 
  // Rest of the code follows ...
 
endclass

uvm_sequencer的源代码：

// Definition of uvm_sequencer
class uvm_sequencer #(type REQ=uvm_sequence_item, RSP=REQ)
                                   extends uvm_sequencer_param_base #(REQ, RSP);
  // Variable: seq_item_export
  // This export provides access to this sequencer's implementation of the
  // sequencer interface.
 
  uvm_seq_item_pull_imp #(REQ, RSP, this_type) seq_item_export;
 
  // Rest of the class contents follow ...
 
endclass