2174: Accumulator 计算从0加到n共有多少位发生过变化

本文介绍了一种计算从初始状态到目标状态过程中,计数器内部二进制表示发生变化的位数的方法,并提供了一个C++实现示例。

2174: Accumulator


ResultTIME LimitMEMORY LimitRun TimesAC TimesJUDGE
3s8192K324109Standard
Accumulator can be used to count the number of the objects. Initially, the value of accumulator is set to zero. After each objected is counted, the value of accumulator will increase by one. At the end, the value of accumulator is the total number of the objects counted. The number shown on the accumulator is in decimal form between 0 and 1000000000, however, inside the accumulator, the number is represented using 32bit binaries. The initial value of the accumulator is 32 zeros. Like below

00000000000000000000000000000000

You need to modify the binaries using the following method. Suppose a binary t of the length 32 bit, each bit can be represented with t[i] (0 <= i < 32). Of course, i=0 is the lowest bit.

i=0;
s=0;
while(t[i]!=0)
{
    t[i]=0;
    i++;
    s++;
}
t[i]=1;
s++;
The total bits that need to be modifed to change from current number to next number is the value of s.
EG.
DEC		Bin
8        0000000000000000000000000000111
9        0000000000000000000000000001000 

You need to change 4 bits. The input to this problem is the final result of the accumulator(in decimal format), please calculate how many bits changed during the accumulation.

Sample Input

4

Sample Output

7
赵大牛找的规律,膜拜一下
#include<iostream>
#include<cstdio>
using namespace std;
int count_1(int n)//求n的二进制中有几个1
{
    int cnt;
    for(cnt = 0; n; n >>= 1)
    {
         cnt += n & 1;
     }
    return cnt;
}
int main()
{
    int n;
    while(scanf("%d",&n)==1)
    {
        int cnt=n*2-count_1(n);
        printf("%d/n",cnt);
    }
    return 0;
}
module Efficient_FIR ( input wire clk, // 50MHz系统时钟 input wire rst_n, // 系统复 input wire [1:0] current_rate, // 采样率选择: 00=44.1kHz, 01=48kHz, 10=96kHz input wire [15:0] data_in, // 16输入数据 input wire data_valid, // 输入数据有效标志 input wire [15:0] coeff_data, // 系数数据输入 output reg [10:0] coeff_addr, // 系数地址 output reg [31:0] data_out, // 32滤波输出 output reg data_out_valid // 输出有效标志 ); // 滤波器阶数定义(根据采样率) parameter ORDER_44K = 1533; // 44.1kHz对应阶数 parameter ORDER_48K = 835; // 48kHz对应阶数 parameter ORDER_96K = 240; // 96kHz对应阶数 // 状态机定义 typedef enum logic [2:0] { INIT, // 初始化状态 LOAD_COEFFS, // 加载系数 WAIT_DATA, // 等待数据 PROCESS, // 处理数据 OUTPUT_RESULT // 输出结果 } state_t; // 内部信号声明 reg [2:0] state, next_state; reg [10:0] order; // 当前阶数 reg [10:0] coeff_counter; // 系数计数器 reg [10:0] data_counter; // 数据计数器 reg [31:0] accumulator; // 累加器 reg [15:0] data_buffer [0:2047]; // 数据缓冲区(支持最大阶数) reg [15:0] coeff_buffer [0:2047]; // 系数缓冲区 reg rate_changed; // 采样率变化标志 reg [1:0] prev_rate; // 前一个采样率值 reg processing_start; // 处理开始标志 // 采样率检测与阶数设置 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin order <= 0; prev_rate <= 2'b00; rate_changed <= 1'b0; end else begin prev_rate <= current_rate; rate_changed <= (current_rate != prev_rate); case (current_rate) 2'b00: order <= ORDER_44K; // 44.1kHz 2'b01: order <= ORDER_48K; // 48kHz 2'b10: order <= ORDER_96K; // 96kHz default: order <= ORDER_44K; // 默认44.1kHz endcase end end // 状态机主控 always @(posedge clk or negedge rst_n) begin if (!rst_n) begin state <= INIT; end else begin state <= next_state; end end // 状态转移逻辑 (关键修复1) always_comb begin next_state = state; case (state) INIT: next_state = LOAD_COEFFS; LOAD_COEFFS: if (coeff_counter >= order - 1) // 修复比较条件 next_state = WAIT_DATA; else if (rate_changed) next_state = INIT; WAIT_DATA: if (data_valid) next_state = PROCESS; else if (rate_changed) next_state = INIT; PROCESS: if (data_counter >= order - 1) // 修复比较条件 next_state = OUTPUT_RESULT; OUTPUT_RESULT: next_state = WAIT_DATA; endcase end // 系数加载逻辑 (关键修复2) always @(posedge clk or negedge rst_n) begin if (!rst_n) begin coeff_counter <= 0; coeff_addr <= 0; end else begin case (state) INIT: begin coeff_counter <= 0; coeff_addr <= 0; end LOAD_COEFFS: begin if (coeff_counter < order) begin coeff_addr <= coeff_counter; coeff_buffer[coeff_counter] <= coeff_data; coeff_counter <= coeff_counter + 1; end end default: coeff_addr <= 0; endcase end end // 数据处理逻辑 (关键修复3) always @(posedge clk or negedge rst_n) begin if (!rst_n) begin data_counter <= 0; accumulator <= 0; data_out <= 0; data_out_valid <= 0; processing_start <= 0; end else begin data_out_valid <= 0; // 默认无效 case (state) WAIT_DATA: begin // 仅当进入该状态时初始化计数器 if (state != next_state) begin data_counter <= 0; accumulator <= 0; processing_start <= 1; end // 当数据有效时,存储新数据并移 if (data_valid) begin // 移数据缓冲区 (优化实现) for (int i = 2046; i >= 0; i = i - 1) data_buffer[i + 1] <= data_buffer[i]; data_buffer[0] <= data_in; end end PROCESS: begin if (processing_start) begin processing_start <= 0; // 初始化第一个乘加操作 accumulator <= $signed(data_buffer[0]) * $signed(coeff_buffer[0]); data_counter <= 1; end else if (data_counter < order) begin // 执行乘加操作 accumulator <= accumulator + ($signed(data_buffer[data_counter]) * $signed(coeff_buffer[data_counter])); data_counter <= data_counter + 1; end end OUTPUT_RESULT: begin // 输出最终结果 data_out <= accumulator; data_out_valid <= 1'b1; end endcase end end endmodule 为什么没有输出呢,先是全部都是0,在第一次data_out_valid后全部变成了XXXXXX
最新发布
11-23
评论
成就一亿技术人!
拼手气红包6.0元
还能输入1000个字符
 
红包 添加红包
表情包 插入表情
 条评论被折叠 查看
添加红包

请填写红包祝福语或标题

红包个数最小为10个

红包金额最低5元

当前余额3.43前往充值 >
需支付:10.00
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明:

1.余额是钱包充值的虚拟货币,按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载,可以购买VIP、付费专栏及课程。

余额充值