VHDL借助十进制计数器实现100进制计数器 74160

最新推荐文章于 2021-07-14 20:41:50 发布

koala_cola

最新推荐文章于 2021-07-14 20:41:50 发布

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本文链接：https://blog.youkuaiyun.com/koala_cola/article/details/106905004

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本文介绍了一种使用VHDL语言实现的100进制计数器设计，通过两个子计数器模块的级联实现。设计中包含了时钟输入、复位信号、置位信号以及输出信号等关键部分，适用于数字电路设计和FPGA开发。

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count100 IS
port
(
	clk:in std_logic;
	rco:out std_logic
);
end;

architecture dataflow of count100 is
SIGNAL RCO1:STD_logic;
SIGNAL RCO2:STD_logic;
SIGNAL RCOTEMP:STD_logic;
SIGNAL RCOTEMP2:STD_logic;
COMPONENT counter10 is
port
(clk,res,set: in std_logic;
d:in std_logic_vector(3 downto 0);
p,t:std_logic;
c: out std_logic_vector(3 downto 0);
cout:out std_logic;
temp:buffer std_logic_vector(3 downto 0)
);
end COMPONENT;
BEGIN

RCO<=RCO1 AND RCO2;
COUNT1: COUnter10 PORT MAP(clk=>clk,P=>'1',T=>'1',COUT=>RCO1,res=>'1',set=>'1',d=>"0000");
COUNT2: COUnter10 PORT MAP(clk=>clk,P=>RCO1,T=>'1',COUT=>RCO2,res=>'1',set=>'1',d=>"0000");
END;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count100 IS
port
(
	clk:in std_logic;
	rco:out std_logic
);
end;

architecture dataflow of count100 is
SIGNAL RCO1:STD_logic;
SIGNAL RCO2:STD_logic;
SIGNAL RCOTEMP:STD_logic;
SIGNAL RCOTEMP2:STD_logic;
COMPONENT counter10 is
port
(clk,res,set: in std_logic;
d:in std_logic_vector(3 downto 0);
p,t:std_logic;
c: out std_logic_vector(3 downto 0);
cout:out std_logic;
temp:buffer std_logic_vector(3 downto 0)
);
end COMPONENT;
BEGIN

RCO<=RCO1 AND RCO2;
COUNT1: COUnter10 PORT MAP(clk=>clk,P=>'1',T=>'1',COUT=>RCO1,res=>'1',set=>'1',d=>"0000");
COUNT2: COUnter10 PORT MAP(clk=>clk,P=>RCO1,T=>'1',COUT=>RCO2,res=>'1',set=>'1',d=>"0000");
END;