sysgen 对带parameter的verilog封装blackbox的问题

例如这样一个小模块

module mul#(
parameter MUL_A_WIDTH = 10,
parameter MUL_B_WIDTH = 10,
parameter MUL_C_WIDTH =  MUL_A_WIDTH+MUL_B_WIDTH-1
)

(
input [MUL_A_WIDTH-1:0] a,
input [MUL_B_WIDTH-1:0] b,
output [MUL_C_WIDTH-1:0] c
);

assign c = a*b;

endmodule

 

封装进blackbox后，对其.m进行修改

function mul_config(this_block)

  % Revision History:
  %
  %   29-Jan-2019  (09:34 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     E:\BLE\mul.v
  %
  %

  this_block.setTopLevelLanguage('Verilog');

  this_block.setEntityName('mul');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagA