本文探讨了DDR2内存控制器的内部数据总线时钟频率和DDR2总线时钟频率如何直接影响最大吞吐量。DDR2总线时钟频率为CLKIN2频率的十倍，而内部数据总线时钟频率固定为CPU频率的三分之一。最大吞吐量由这两个频率中的较小者决定。例如，若内部数据总线频率为333MHz（CPU频率为1GHz），而DDR2总线频率为267MHz（CLKIN2频率为26.7MHz），则DDR2内存控制器的最大数据速率可达2.1GB/s。
The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum
throughput of the DDR2 bus. The clock frequency of the DDR2 bus is equal to the CLKIN2 frequency
multiplied by 10. The internal data bus clock frequency of the DDR2 Memory Controller is fixed at a
divide-by-three ratio of the CPU frequency. The maximum DDR2 throughput is determined by the smaller
of the two bus frequencies. For example, if the internal data bus frequency is 333 MHz (CPU frequency is
1 GHz) and the DDR2 bus frequency is 267 MHz (CLKIN2 frequency is 26.7 MHz), the maximum data
rate achievable by the DDR2 memory controller is 2.1 Gbytes/sec. The DDR2 bus is designed to sustain a
maximum throughput of up to 2.1 Gbytes/sec at a 533-MHz data rate (267-MHz clock rate), as long as
data requests are pending in the DDR2 Memory Controller.
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