[Design]Step by Step

本文分享了一次应用设计的经验教训,作者最初将所有功能挤在一个页面上导致诸多问题。随后通过将功能拆分为多个页面(如图片选择页、角色创建页和结果展示页),有效地减少了模块间的意外交互,使代码更加清晰易维护。

Anytime when designing an application, try your best to split the work into steps. Don't put every functions into one workspace.

For example, in our project, users can select an image from the image list and then create their character based on the selected image.

Initially, I didn't do any design work. I just listed all the functions that needed and split the whole workspace - the web page - into different areas: one for image list, one for user editing and one for control buttons.

After I implemented those functions and put them together, trucks of problems came! What will happen when user clicks a new image without store existing work? How to make it efficient when users only click images and never do editing? Should we restore everything to the initial state or keep the original state when users click a new image? Bla bla ...

To handle those interaction between all the areas makes the code really confusing. What should I do?

Stop! Try a new way.

Finally, I use different pages to host different functions. A page for users to select an image, a page to create the character and a page to show the result after handing in. In this way, I can avoid many accidental interaction between modules. Only limited interactions are allowed. A nice way!

Original:

Capture1

Redesigned:

Capture2 Capture3

在 CCS 12 中使用 STEP 功能进行 CLB(Configurable Logic Block)仿真时,若提示 `Build of the CLB simulation has moved to the CLB Tool`,则表明仿真构建流程已从 CCS 移至 TI 提供的专用 CLB 工具链。用户需要通过 SysConfig 中的配置触发仿真文件生成,并确保相关环境变量和工具链正确配置。 首先,在 SysConfig 中打开目标设备的 CLB 模块配置界面,进入 **"Global Parameters"** 部分,找到 **"Tile Design"** 子模块,并启用 **"Generate CLB Simulation File"** 选项。此时,工具会生成 `clb_sim.c`、`clb_sim.h` 和 `clb_sim_model.v` 文件,用于后续仿真流程。此操作是必须的,因为 CCS 不再直接支持 CLB 仿真的构建[^1]。 接下来,确保系统环境变量 `CLB_SIM_COMPILER` 已正确设置,指向支持目标平台的 GCC 编译器路径。若未正确配置,可能会导致生成 `.out` 文件后仍无法生成 `simulation_output.exe` 或 `clb.vcd` 文件。建议使用 TDM-GCC 5.1.0 版本,可从指定地址下载并安装[^3]。 此外,在 CCS 工程中,右键点击工程并选择 **Properties for clb_empty → Build → Variables**,将 `CLB_DEBUG` 和 `GENERATE_DIAGRAM` 均设置为 `1`,以便在仿真过程中生成调试信息和框图显示[^2]。该设置有助于验证 TILE 设计的逻辑结构和信号流向。 完成上述配置后,重新构建工程,并运行仿真。仿真结果可通过 Tcl 脚本进行分析和报告生成,例如: ```tcl # 分析仿真结果并生成报告 set sim_results [get_simulation_results] extract_waveforms $sim_results plot_waveforms $sim_results generate_report $sim_results > "simulation_report.txt" ``` 该脚本可用于提取波形数据、绘制信号变化,并输出文本格式的仿真报告[^3]。 ---
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